Abstract is missing.
- Synthesis of programs from temporal property specificationsAmir Pnueli, Uri Klein. 1-7 [doi]
- Bang for the buck: Improvising and scheduling verification engines for effective resource utilizationMalay K. Ganai, Weihong Li. 8-17 [doi]
- Refining schizophrenia via graph reachability in EsterelJeong-Han Yun, Chul-Joo Kim, Sunae Seo, Taisook Han, Kwang-Moo Choe. 18-27 [doi]
- The role of mutation analysis for property qualificationLuigi Di Guglielmo, Franco Fummi, Graziano Pravadelli. 28-35 [doi]
- Incremental modelling and verification of the PCI Express transaction layerPeter Böhm. 36-45 [doi]
- Verification of an industrial SystemC/TLM model using LOTOS and CADPHubert Garavel, Claude Helmstetter, Olivier Ponsini, Wendelin Serwe. 46-55 [doi]
- High-level optimization of integer multipliers over a finite bit-width with verification capabilitiesO. Sarbishei, M. Tabandeh, Bijan Alizadeh, Masahiro Fujita. 56-65 [doi]
- 2009 MEMOCODE Co-Design ContestForrest Brewer, James C. Hoe. 66-68 [doi]
- A design case study: CPU vs. GPGPU vs. FPGADaniel L. Rosenband, Till Rosenband. 69-72 [doi]
- Implementing a fast cartesian-polar matrix interpolatorAbhinav Agarwal, Nirav Dave, Kermin Fleming, Asif Khan, Myron King, Man Cheuk Ng, Muralidaran Vijayaraghavan. 73-76 [doi]
- Can we computerize an elephant?David Harel. 77 [doi]
- Multicore power management: Ensuring robustness via early-stage formal verificationAnita Lungu, Pradip Bose, Daniel J. Sorin, Steven German, Geert Janssen. 78-87 [doi]
- A cross-layer approach to heterogeneity and reliabilityDaniel W. Williams, Aprotim Sanyal, Dan Upton, Jason Mars, Sudeep Ghosh, Kim M. Hazelwood. 88-97 [doi]
- Implementing a high-performance multithreaded microprocessor: A case study in high-level design and validationEric S. Chung, James C. Hoe. 98-107 [doi]
- An introduction to implementation attacks and countermeasuresThomas Popp. 108-115 [doi]
- Survival strategies for synthesized hardware systemsMartin C. Rinard. 116-120 [doi]
- Codesign of dependable systems: A component-based modeling languageMarco Bozzano, Alessandro Cimatti, Marco Roveri, Joost-Pieter Katoen, Viet Yen Nguyen, Thomas Noll. 121-130 [doi]
- Performance estimation for task graphs combining sequential path profiling and control dependence regionsFabrizio Ferrandi, Marco Lattuada, Christian Pilato, Antonino Tumeo. 131-140 [doi]
- Combining control and data abstraction in the verification of hybrid systemsXavier Briand, Bertrand Jeannet. 141-150 [doi]
- Buffer sharing in CSP-like programsNalini Vasudevan, Stephen A. Edwards. 151-160 [doi]
- Static data-flow analysis of synchronous programsJens Brandt, Klaus Schneider. 161-170 [doi]
- Bounded Dataflow Networks and Latency-Insensitive circuitsMuralidaran Vijayaraghavan, Arvind. 171-180 [doi]