Abstract is missing.
- Machine Learning-based Fast Circuit Simulation for Analog Circuit ArrayJaeseung Lee, Sejin Park, Minhyeok Kweon, Seokhyeong Kang. 1-6 [doi]
- Early Identification of Timing Critical RTL Components using ML based Path Delay PredictionPrianka Sengupta, Aakash Tyagi, Yiran Chen 0001, Jiang Hu. 1-6 [doi]
- DepthGraphNet: Circuit Graph Isomorphism Detection via Siamese-Graph Neural NetworksFin Amin, Soumyadeep Chatterjee, Paul D. Franzon. 1-6 [doi]
- Machine Learning in EDA: When and HowBei Yu 0001. 1-6 [doi]
- NeuroPDR: Integrating Neural Networks in the PDR Algorithm for Hardware Model CheckingGuangyu Hu, Wei Zhang, Hongce Zhang. 1-6 [doi]
- Characterize the ability of GNNs in attacking logic lockingWei Li, Ruben Purdy, José M. F. Moura, R. D. Shawn Blanton. 1-6 [doi]
- AI-EDA: Toward a Holistic Approach to AI-Powered EDAYoungsoo Shin. 1-3 [doi]
- ChatEDA: A Large Language Model Powered Autonomous Agent for EDAZhuolun He, Haoyuan Wu, Xinyun Zhang, Xufeng Yao, Su Zheng, Haisheng Zheng, Bei Yu 0001. 1-6 [doi]
- Analog synthesis 3.0: AI/ML to synthesize and test analog ICs: hope or hype ?Georges Gielen. 1 [doi]
- ML-TCAD: Perspectives and Challenges on Accelerating Transistor Modeling using MLRodion Novkin, Simon Thomann, Hussam Amrouch. 1-4 [doi]
- Simultaneous Clock Wire Sizing and Shield Insertion for Minimizing Routing BlockageYoonsang Song, Gangmin Cho, Wonjae Lee, Youngsoo Shin. 1-6 [doi]
- Routability-Driven Power Distribution Network Synthesis with IR-Drop BudgetingWonjae Lee, Insu Cho, Gangmin Cho, Youngsoo Shin. 1-6 [doi]
- The 2023 MLCAD FPGA Macro Placement Benchmark Design Suite and Contest ResultsIsmail Bustany, Grigor Gasparyan, Amit Gupta, Andrew B. Kahng, Meghraj Kalase, Wuxi Li, Bodhisatta Pramanik. 1-6 [doi]
- Using Graph Neural Networks for Timing Estimations of RTL Intermediate RepresentationsDaniela Sanchez Lopera, Ishwor Subedi, Wolfgang Ecker. 1-6 [doi]
- MMM: Machine Learning-Based Macro-Modeling for Linear Analog ICs and ADC/DACsYishuang Lin, Yaguang Li, Meghna Madhusudan, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu. 1-6 [doi]
- ASAP: Accurate Synthesis Analysis and Prediction with Multi-Task LearningYikang Ouyang, Sicheng Li, Dongsheng Zuo, Hanwei Fan, Yuzhe Ma. 1-6 [doi]
- Differentiable Neural Network Surrogate Models for gm/ID-based Analog IC Sizing OptimizationYannick Uhlmann, Till Moldenhauer, Jürgen Scheible. 1-6 [doi]
- Beyond Hyperparameter Optimization: Using AI to address Digital Implementation ChallengesChuck Alpert. 1 [doi]
- ConVERTS: Contrastively Learning Structurally InVariant Netlist RepresentationsAnimesh Basak Chowdhury, Jitendra Bhandari, Luca Collini, Ramesh Karri, Benjamin Tan 0001, Siddharth Garg. 1-6 [doi]
- APEX: Recommending Design Flow Parameters Using a Variational AutoencoderMichael Kazda, Michael D. Monkowski, George Antony. 1-6 [doi]
- Optimizing Constrained Random Verification with ML and Bayesian EstimationBhuvnesh Kumar, Ganapathy Parthasarathy, Saurav Nanda, Sridhar Rajakumar. 1-6 [doi]
- Chip-Chat: Challenges and Opportunities in Conversational Hardware DesignJason Blocklove, Siddharth Garg, Ramesh Karri, Hammond Pearce. 1-6 [doi]
- Bridging Divides: Unifying AI Architectures from from Edge to CloudIvo Bolsens. 1 [doi]
- Hybrid Utilization of Subgraph Isomorphism and Relational Graph Convolutional Networks for Analog Functional Grouping AnnotationZhengfeng Wu, Isabel Song, Ioannis Savidis. 1-6 [doi]
- A Robust Routing Guide Generation Approach for Mixed-Size DesignsZhi-Hong Lee, Chen-Han Lu, Hsin-Hung Pan, Ting-Chi Wang, Po-Yuan Chen, Cindy Chin-Fang Shen. 1-6 [doi]
- ML-augmented Simulation and Co-optimization for Semiconductor Applications and Design WorkflowsBeyondNorman Chang. 1 [doi]