Abstract is missing.
- Design for VerifiabilityGeorge J. Milne. 1-13
- Verification of Synchronous Circuits by Symbolic Logic SimulationRandal E. Bryant. 14-24
- Constraints, Abstraction and VerificationDaniel Weise. 25-39
- Formalising the Design of an SECD chipBrian T. Graham, Graham M. Birtwistle. 40-66
- Reasoning about State Machines in Higher-Order LogicPaul Loewenstein. 67-89
- A Mechanically Derived Systolic Implementation of Pyramid InitializationChristian Lengauer, Bikash Sabata, Farshid Arman. 90-105
- Behavior-Preserving Transformations for High-Level SynthesisRaul Camposano. 106-128
- From Programs to Transistors: Verifying Hardware Synthesis ToolsGeoffrey M. Brown, Miriam Leeser. 129-151
- Combining Engineering Vigor with Mathematical RigorShiu-Kai Chin. 152-176
- Totally Verified Systems: Linking Verified Software to Verified HardwareJeffrey J. Joyce. 177-201
- What s in a Timing Discipline? Considerations in the Specification and Synthesis of Systems with Interacting Asynchronous and Synchronous ComponentsP. A. Subrahmanyam. 202-223
- Complete Trace StructuresDavid L. Dill. 224-243
- The Design of a Delay-Insensitive Microprocessor: An Example of Circuit Synthesis by Program TransformationAlain J. Martin. 244-259
- Manipulating Logical Organization with System FactorizationsSteven D. Johnson. 260-281
- The Verification of a Bit-slice ALUWarren A. Hunt Jr., Bishop Brock. 282-306
- Verification of a Pipelined Microprocessor Using ClioMark Bickford, Mandayam K. Srivas. 307-332
- Verification Of Combinational Logic in NuprlDavid A. Basin, Peter Del Vecchio. 333-357
- Veritas:::+:::: A Specification Language Based on Type TheoryF. Keith Hanna, Neil Daeche, Mark Longley. 358-379
- Categories for the Working Hardware DesignerMary Sheeran. 380-402