Abstract is missing.
- Improve the Verification Productivity: Some Best Practices from SoC and Processor ProjectsWeihua Han. 1-3 [doi]
- A Case Study of Multiprocessor Bugs Found Using RIS Generators and Memory Usage TechniquesDeepak Venkatesan, Pradeep Nagarajan. 4-9 [doi]
- Fast Simulation of Pipeline in ASIP SimulatorsZdenek Prikryl. 10-15 [doi]
- Automatic UVM Environment Generation for Assertion-Based and Functional Verification of SystemC DesignsMichael Mefenza, Franck Yonga, Christophe Bobda. 16-21 [doi]
- Optimized Simulation Acceleration with Partial Testbench EvaluationSomnath Banerjee, Tushar Gupta. 22-27 [doi]
- 'Dump What You Need' - A Coverage Methodology to Accelerate SoC VerificationGanesh Venkatakrishnan, Naresh Kumar Kadali. 28-32 [doi]
- Hardware Synthesis from Software-Oriented UML DescriptionsMichele Lora, Francesco Martinelli, Franco Fummi. 33-38 [doi]
- Embracing the FPGA Challenge for Processor Design VerificationNitin Gupta, Chethan Harakchand. 39-43 [doi]
- An FPGA Based Ecosystem for USBPHY ValidationManeesh Kumar Pandey, Shwetank Shekhar, Amit Sinha, Arun Mishra. 44-48 [doi]
- Mutation Based Feature LocalizationJan Malburg, Emmanuelle Encrenaz-Tiphène, Görschwin Fey. 49-54 [doi]
- System Verilog Assertion Debugging Based on Visualization, Simulation Results, and MutationMoaz Mostafa, Mona Safar, M. Watheq El-Kharashi, Mohamed Dessouky. 55-60 [doi]
- A Novel Approach for SVA Generation of DDR Memory Protocols Based on TDMLMohamed O. Kayed, Mohamed AbdElSalam, Rafik Guindi. 61-66 [doi]
- JTAG-AXI Debug IP with Performance Meter ModeMrugesh Walimbe. 67-69 [doi]
- Continuous Linting with Automatic DebugDaniel Hansson. 70-72 [doi]
- A Random Instruction Sequence Generator for ARM Based SystemsShajid Thiruvathodi, Deepak Yeggina. 73-77 [doi]
- Directed Test Case Generation for x86 Instruction DecodingPeter-Michael Seidel. 78-82 [doi]
- Using Formal Verification of Parameterized Systems in RAW Hazard Analysis in MicroprocessorsLukás Charvát, Ales Smrcka, Tomás Vojnar. 83-89 [doi]
- A Case for Multi-level Combination of Theorem Proving and Model Checking ToolsPeter-Michael Seidel. 90-97 [doi]
- A Configurable Random Instruction Sequence (RIS) Tool for Memory Coherence in Multi-processor SystemsJohn Hudson, Gunaranjan Kurucheti. 98-101 [doi]
- Synthesizable Memory Models for Virtual PrototypingParikshit Pritam Dhodapkar. 102-104 [doi]
- FIES: A Fault Injection Framework for the Evaluation of Self-Tests for COTS-Based Safety-Critical SystemsAndrea Höller, Gerhard Schonfelder, Nermin Kajtazovic, Tobias Rauter, Christian Kreiner. 105-110 [doi]