Abstract is missing.
- Efficient routing implementation in complex systems-on-chipJosé Cano, José Flich, José Duato, Marcello Coppola, Riccardo Locatelli. 1-8 [doi]
- Analysis of application-aware on-chip routing under traffic uncertaintyNithin Michael, Milen Nikolov, Ao Tang, G. Edward Suh, Christopher Batten. 9-16 [doi]
- HOPE: Hotspot congestion control for Clos network on chipNajla Alfaraj, Junjie Zhang, Yang Xu, H. Jonathan Chao. 17-24 [doi]
- Automatic verification for deadlock in networks-on-chips with adaptive routing and wormhole switchingFreek Verbeek, Julien Schmaltz. 25-32 [doi]
- Deadlock-free fine-grained thread migrationMyong Hyon Cho, Keun Sup Shim, Mieszko Lis, Omer Khan, Srinivas Devadas. 33-40 [doi]
- Prevention flow-control for low latency torus networks-on-chipArpit Joshi, Madhu Mutyam. 41-48 [doi]
- A vertical bubble flow network using inductive-coupling for 3-D CMPsHiroki Matsutani, Yasuhiro Take, Daisuke Sasaki, Masayuki Kimura, Yuki Ono, Yukinori Nishiyama, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano. 49-56 [doi]
- Optimal network architectures for minimizing average distance in k-ary n-dimensional mesh networksMatt Grange, Roshan Weerasekera, Dinesh Pamunuwa, Axel Jantsch, Awet Yemane Weldezion. 57-64 [doi]
- Congestion aware, fault tolerant, and thermally efficient inter-layer communication scheme for hybrid NoC-bus 3D architecturesAmir-Mohammad Rahmani, Pasi Liljeberg, Khalid Latif 0002, Juha Plosila, Kameswar Rao Vaddina, Hannu Tenhunen. 65-72 [doi]
- Exploring partitioning methods for 3D Networks-on-Chip utilizing adaptive routing modelMasoumeh Ebrahimi, Masoud Daneshtalab, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen. 73-80 [doi]
- BLOCON: A Bufferless Photonic Clos network-on-chip architectureYu-Hsiang Kao, H. Jonathan Chao. 81-88 [doi]
- Two-hop Free-space based optical interconnects for chip multiprocessorsAhmed Abousamra, Rami G. Melhem, Alex K. Jones. 89-96 [doi]
- All-optical wavelength-routed NoC based on a novel hierarchical topologySomayyeh Koohi, Meisam Abdollahi, Shaahin Hessabi. 97-104 [doi]
- Exploiting inherent information redundancy to manage transient errors in NoC routing arbitrationQiaoyan Yu, Meilin Zhang, Paul Ampadu. 105-112 [doi]
- A distributed and topology-agnostic approach for on-line NoC testingMohammad Reza Kakoee, Valeria Bertacco, Luca Benini. 113-120 [doi]
- Energy and reliability oriented mapping for regular Networks-on-ChipCristinel Ababei, Hamed Sajjadi Kia, Om Prakash Yadav, Jingcao Hu. 121-128 [doi]
- Online task remapping strategies for fault-tolerant Network-on-Chip multiprocessorsOnur Derin, Deniz Kabakci, Leandro Fiorin. 129-136 [doi]
- FIST: A fast, lightweight, FPGA-friendly packet latency estimator for NoC modeling in full-system simulationsMichael Papamichael, James C. Hoe, Onur Mutlu. 137-144 [doi]
- DART: A programmable architecture for NoC simulation on FPGAsDanyao Wang, Natalie D. Enright Jerger, J. Gregory Steffan. 145-152 [doi]
- Inferring packet dependencies to improve trace based simulation of on-chip networksChristopher Nitta, Kevin Macdonald, Matthew K. Farrens, Venkatesh Akella. 153-160 [doi]
- Delay analysis of wormhole based heterogeneous NoCYaniv Ben-Itzhak, Israel Cidon, Avinoam Kolodny. 161-168 [doi]
- Complex network inspired fault-tolerant NoC architectures with wireless linksAmlan Ganguly, Paul Wettin, Kevin Chang, Partha Pratim Pande. 169-176 [doi]
- Design of multi-channel wireless NoC to improve on-chip communication capacity!Dan Zhao, Yi Wang, Jian Li, Takamaro Kikkawa. 177-184 [doi]
- Link pipelining strategies for an application-specific asynchronous NoCDaniel Gebhardt, JunBok You, Kenneth S. Stevens. 185-192 [doi]
- A low-latency adaptive asynchronous interconnection network using bi-modal router nodesGennette Gill, Sumedh S. Attarde, Geoffray Lacourba, Steven M. Nowick. 193-200 [doi]
- Dynamic decentralized mapping of tree-structured applications on NoC architecturesAndreas Weichslgartner, Stefan Wildermann, Jürgen Teich. 201-208 [doi]
- Cross clock-domain TDM virtual circuits for networks on chipsZhonghai Lu. 209-216 [doi]
- VLSI micro-architectures for high-radix crossbar schedulersGiorgos Passas, Manolis Katevenis, Dionisios N. Pnevmatikatos. 217-224 [doi]
- Interconnect Physical Analyser (IPAA) applied to the design of scalable Network-on-Chip interconnect for Cryptographic acceleratorsTom English, Emanuel M. Popovici. 225-232 [doi]
- Reducing network-on-chip energy consumption through spatial locality speculationHyungJun Kim, Pritha Ghoshal, Boris Grot, Paul V. Gratz, Daniel A. Jimenez. 233-240 [doi]
- Curbing energy cravings in networks: A cross-sectional view across the micro-macro boundaryAmlan Ganguly, Partha Kundu, Pradip Bose. 241-246 [doi]
- Challenges and promises of nano and bio communication networksChristof Teuscher, Cristian Grecu, Ting Lu, Ron Weiss. 247-254 [doi]
- The XMOS XK-XMP-64 development boardJames Hanlon. 255-256 [doi]
- Dynamic power management of voltage-frequency island partitioned Networks-on-Chip using Intel s Single-chip Cloud ComputerRadu David, Paul Bogdan, Radu Marculescu, Ümit Y. Ogras. 257-258 [doi]
- A software framework for trace analysis targeting multicore platforms designGuopeng Wei, Paul Bogdan, Radu Marculescu. 259-260 [doi]
- Reconfiguration of a 3GPP-LTE telecommunication application on a 22-core NoC-based system-on-chipFabien Clermidy, N. Cassiau, N. Coste, D. Dutoit, M. Fantini, Dimitri Ktenas, Romain Lemaire, L. Stefanizzi. 261-262 [doi]
- A comprehensive Networks-on-Chip simulator for error control explorationsQiaoyan Yu, Meilin Zhang, Paul Ampadu. 263-264 [doi]
- NoCs simulation framework for OMNeT++Yaniv Ben-Itzhak, Eitan Zahavi, Israel Cidon, Avinoam Kolodny. 265-266 [doi]
- Spidergon STNoC design flowFlorentine Dubois, José Cano, Marcello Coppola, José Flich, Frédéric Pétrot. 267-268 [doi]