Abstract is missing.
- MinBD: Minimally-Buffered Deflection Routing for Energy-Efficient InterconnectChris Fallin, Greg Nazario, Xiangyao Yu, Kevin Kai-Wei Chang, Rachata Ausavarungnirun, Onur Mutlu. 1-10 [doi]
- Déjà Vu Switching for Multiplane NoCsAhmed Abousamra, Rami G. Melhem, Alex K. Jones. 11-18 [doi]
- HARAQ: Congestion-Aware Learning Model for Highly Adaptive Routing Algorithm in On-Chip NetworksMasoumeh Ebrahimi, Masoud Daneshtalab, Fahimeh Farahnakian, Juha Plosila, Pasi Liljeberg, Maurizio Palesi, Hannu Tenhunen. 19-26 [doi]
- Overlaid Mesh Topology Design and Deadlock Free Routing in Wireless Network-on-ChipDan Zhao, Ruizhe Wu. 27-34 [doi]
- An Optimal Control Approach to Power Management for Multi-Voltage and Frequency Islands Multiprocessor Platforms under Highly Variable WorkloadsPaul Bogdan, Radu Marculescu, Siddharth Jain, Rafael Tornero Gavila. 35-42 [doi]
- In-network Monitoring and Control Policy for DVFS of CMP Networks-on-Chip and Last Level CachesXi Chen, Zheng Xu, HyungJun Kim, Paul Gratz, Jiang Hu, Michael Kishinevsky, Ümit Y. Ogras. 43-50 [doi]
- Modeling and Power Evaluation of On-Chip Router Components in SpintronicsPierre Schamberger, Zhonghai Lu, Xianyang Jiang, Meikang Qiu. 51-58 [doi]
- Heterogeneous NoC Design for Efficient Broadcast-based Coherence Protocol SupportMario Lodde, Jose Flich, Manuel E. Acacio. 59-66 [doi]
- CCNoC: Specializing On-Chip Interconnects for Energy Efficiency in Cache-Coherent ServersStavros Volos, Ciprian Seiculescu, Boris Grot, Naser Khosro Pour, Babak Falsafi, Giovanni De Micheli. 67-74 [doi]
- Synthesis of NoC Interconnects for Custom MPSoC ArchitecturesGul N. Khan, Anita Tino. 75-82 [doi]
- Hierarchical Network-on-Chip and Traffic Compression for Spiking Neural Network ImplementationsSnaider Carrillo, Jim Harkin, L. J. McDaid, Sandeep Pande, Seamus Cawley, Brian McGinley, Fearghal Morgan. 83-90 [doi]
- Reservation-based Network-on-Chip Timing Models for Large-scale Architectural SimulationJavier Navaridas, Behram Khan, Salman Khan, Paolo Faraboschi, Mikel Luján. 91-98 [doi]
- TOPAZ: An Open-Source Interconnection Network Simulator for Chip Multiprocessors and SupercomputersPablo Abad, Pablo Prieto, Lucia G. Menezo, Adrian Colaso, Valentin Puente, José-Ángel Gregorio. 99-106 [doi]
- Analytical Performance Modeling of Hierarchical Interconnect FabricsNikita Nikitin, Javier de San Pedro, Josep Carmona, Jordi Cortadella. 107-114 [doi]
- Dynamic Flow Regulation for IP Integration on Network-on-ChipZhonghai Lu, Yi Wang. 115-123 [doi]
- A Novel Flit Serialization Strategy to Utilize Partially Faulty Links in Networks-on-ChipChanglin Chen, Ye Lu, Sorin Dan Cotofana. 124-131 [doi]
- Fine-Grained Bandwidth Adaptivity in Networks-on-Chip Using Bidirectional ChannelsRobert Hesse, Jeff Nicholls, Natalie D. Enright Jerger. 132-141 [doi]
- Efficient Timing Channel Protection for On-Chip NetworksYao Wang, G. Edward Suh. 142-151 [doi]
- A Statically Scheduled Time-Division-Multiplexed Network-on-Chip for Real-Time SystemsMartin Schoeberl, Florian Brandner, Jens Sparsø, Evangelia Kasapaki. 152-160 [doi]
- A Mixed Verification Strategy Tailored for Networks on ChipGeorgios Tsiligiannis, Laurence Pierre. 161-168 [doi]
- Transient and Permanent Error Control for High-End Multiprocessor Systems-on-ChipQiaoyan Yu, José Cano, José Flich, Paul Ampadu. 169-176 [doi]
- Generic Monitoring and Management Infrastructure for 3D NoC-Bus Hybrid ArchitecturesAmir-Mohammad Rahmani, Kameswar Rao Vaddina, Khalid Latif 0002, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen. 177-184 [doi]
- Engineering a Bandwidth-Scalable Optical Layer for a 3D Multi-core Processor with Awareness of Layout ConstraintsLuca Ramini, Davide Bertozzi, Luca P. Carloni. 185-192 [doi]
- A Hybrid Buffer Design with STT-MRAM for On-Chip InterconnectsHyunjun Jang, Baik Song An, Nikhil Kulkarni, Ki Hwan Yum, Eun Jung Kim 0001. 193-200 [doi]
- DSENT - A Tool Connecting Emerging Photonics with Electronics for Opto-Electronic Networks-on-Chip ModelingChen Sun, Chia-Hsin Owen Chen, George Kurian, Lan Wei, Jason E. Miller, Anant Agarwal, Li-Shiuan Peh, Vladimir Stojanovic. 201-210 [doi]