Abstract is missing.
- Unrolled layered architectures for non-surjective finite alphabet iterative decodersOana Boncalo, Valentin Savin, Alexandru Amaricai. 1-5 [doi]
- A 10-bit active RF phase shifter for 5G wireless systemsAlok Sethi, Janne P. Aikio, Rana A. Shaheen, Rehman Akbar, Timo Rahkonen, Aarno Pärssinen. 1-4 [doi]
- An RNS based modular multiplier with reduced complexityShahzad Asif, Mark Vesterbacka. 1-4 [doi]
- Towards a single event upset detector based on COTS FPGAKalle Ngo, Tage Mohammadat, Johnny Öberg. 1-6 [doi]
- High-voltage integrated linear regulator with current sinking capabilities for portable ultrasound scannersGuifre Vendrell Pausas, Pere Llimos Muntal, Ivan H. H. Jørgensen. 1-5 [doi]
- Workload prediction for runtime resource managementMina Niknafs, Ivan Ukhov, Petru Eles, Zebo Peng. 1-5 [doi]
- Design of high-performance E-band SPDT switch and LNA in 0.13 μm SiGe BiCMOS technologyRaju Ahamed, Mikko Varonen, Dristy Parveg, Jan Saijets, Kari Halonen. 1-5 [doi]
- A shared scratchpad memory with synchronization supportHenrik Enggaard Hansen, Emad Jacob Maroun, Andreas Toftegaard Kristensen, Jimmi Marquart, Martin Schoeberl. 1-6 [doi]
- Active charge pumping power-saving technique for SC integratorsJia Sun, Timo Rahkonen. 1-4 [doi]
- Energy-efficient neuromorphic receptors for wide-range temporal patterns of post-synaptic responsesXuefei You, Amir Zjajo, Sumeet S. Kumar, Rene van Leuken. 1-6 [doi]
- Design and analysis of high performance pulse ring VCOAditya Dalakoti, Merritt Miller, Forrest Brewer. 1-5 [doi]
- Three-dimensional millimeter-wave frequency-shift-based CMOS biosensor using vertically stacked LC oscillatorsMaya Matsunaga, Taiki Nakanishi, Atsuki Kobayashi, Kazuo Nakazato, Kiichi Niitsu. 1-6 [doi]
- The effect of DPD bandwidth limitation on EVM for a 28 nm WLAN 802.11ac transmitterOscar Morales Chacon, Ted Johansson, Thomas Flink. 1-4 [doi]
- Power mitigation of a heterogeneous multicore architecture by frequency scaling in an OFDM receiver test caseSajjad Nouri, Jari Nurmi. 1-6 [doi]
- ESD induced EMS problems in digital IOsTimm Ostermann. 1-6 [doi]
- Supporting concurrent memory access in TCF-aware processor architecturesMartti Forsell, Jussi Roivainen, Ville Leppänen, Jesper Larsson Träff. 1-6 [doi]
- Digital centric IF-DAC based heterodyne transmitter architectureOner Hanay, Erkan Bayram, Renato Negra. 1-4 [doi]
- A 1.8mW 450-900MHz ±15ps period jitter programmable multi-output clock generator with high supply noise tolerance in 28-nm CMOS processBhavin Odedara, Srikanth Bojja, Nitin Gupta, Igor Rapoport, Tony Ross, Alik Zelichenok. 1-4 [doi]
- Implementation of a performance optimized database join operation on FPGA-GPU platforms using OpenCLMehdi Roozmeh, Luciano Lavagno. 1-6 [doi]
- Exploration of FPGA architectures for tight coupled accelerators in a 22nm FDSOI technologyHeiner Bauer, Sebastian Höppner, Johannes Partzsch, Dennis Walter, Christian Mayr, Florian Schraut, Holger Eisenreich. 1-6 [doi]
- Analysis of a high-speed PCB designChristian Johansson, Torbjorn Manefjord. 1-4 [doi]
- A 45nm CMOS SOI, four element phased array receiver supporting two MIMO channels for 5GRana A. Shaheen, Rehman Akbar, Alok Sethi, Janne P. Aikio, Timo Rahkonen, Aarno Pärssinen. 1-4 [doi]
- A dependable ASIC architecture with RT-level rollback for controller soft error recoveryKeisuke Inoue. 1-4 [doi]
- Ring-oscillator-based timing generator for ultralow-power applicationsPavel Angelov, Martin Nielsen-Lonn, Atila Alvandpour. 1-4 [doi]
- A capacitance multiplier based on DBTAJiri Vavra. 1-5 [doi]
- CMOS digital design of a trusted virtual sensorMacarena C. Martínez-Rodríguez, Miguel Angel Prada, Piedad Brox, Iluminada Baturone. 1-5 [doi]
- High-level synthesis for reduction of WCET in real-time systemsAndreas Toftegaard Kristensen, Luca Pezzarossa, Jens Sparsø. 1-6 [doi]
- Bi-static environmental SAR radar imagerJ. Havard H. Eriksrod, Kristian Gjertsen Kjelgard, Mathias Tommer, John F. Burkhart, Tor Sverre Lande. 1-6 [doi]
- A single chip 16 GS/s arbitrary waveform generator in 0.13 μm BiCMOS technologyP. Ostrovsky, Klaus Tittelbach-Helmrich, Frank Herzel, Oliver Schrape, G. Fischer, Dietmar Kissinger, P. Borner, A. Loose, D. Hellmann, P. Hartogh. 1-4 [doi]
- Design and implementation of a multi-mode harris corner detector architectureJingui Li, Timo Viitanen, Lin Li, Jarmo Takala, Shuvra S. Bhattacharyya. 1-6 [doi]
- Power efficiency optimization of charge pumps in embedded low voltage NOR flash memorySteve Ngueya W., Julien Mellier, Stephane Ricard, Jean Michel Portal, Hassen Aziza. 1-5 [doi]
- Performance estimation of embedded applications on microcontrollersPriit Ruberg, Keijo Lass, Elvar Liiv, Peeter Ellervee. 1-6 [doi]
- A self-consistent Carleman linearization approach for the design of RF mixer circuitsHarry Weber, Gerald Alexander Koroa, Wolfgang Mathis, Dimitar Delchev, Galia Marinova. 1-4 [doi]
- A highly compact, 16.8 dBm Pgat Ka-band power amplifier in 250 nm SiGe: C BiCMOSIancu Somesanu, Hermann Schumacher. 1-4 [doi]
- Self-oscillating multilevel switched-capacitor DC/DC converter for energy harvestingMartin Nielsen-Lonn, Pavel Angelov, J. Jacob Wikner, Atila Alvandpour. 1-5 [doi]
- Dependability evaluation of SISO control-theoretic power managers for processor architecturesSina Shahosseini, Kasra Moazzemi, Amir M. Rahmani, Nikil D. Dutt. 1-6 [doi]
- Subsampling phase-locked loop behavioural modelling approach for phase noise evaluationPeco Gjurovski, Muh-Dey Wei, Renato Negra. 1-4 [doi]
- A call-up for circuit-switched NoCs in the Dark-Silicon EraSalma Hesham, Diana Goehringer, Mohamed A. Abd El ghany. 1-6 [doi]
- A fully integrated 13 GHz CMOS SOI stacked power amplifier for 5G wireless systemsJanne P. Aikio, Alok Sethi, Rana A. Shaheen, Rehman Akbar, Timo Rahkonen, Aarno Pärssinen. 1-4 [doi]
- Designing a differential 3R-2bit RRAM cell for enhancing read margin in cross-point RRAM arraysMohammadreza Nakhkash, Hossein Bardareh, Farzaneh Zokaee, Hamid R. Zarandi. 1-6 [doi]
- A high-resolution reconfigurable sigma-delta Digital-to-Analog Converter for RF pulse transmission in MRI scannersSohaib A. Qazi, Syed Asmat Ali Shah, Hammad Omer, J. Jacob Wikner. 1-6 [doi]
- Towards software performance estimation based on register-transfer level descriptionsHenning Puttnies, Christoph Niemann, Sascha Rohde, Dirk Timmermann, Joerg Schacht. 1-6 [doi]
- Variable-accuracy bit-serial multiplication with row bypassing for ultra low powerYue Lu, Tom J. Kazmierski. 1-6 [doi]
- Improving microarchitecture design and hardware generation using micro-language IP coresAlexander Antonov, Pavel Kustarev, Sergey Bikovsky. 1-6 [doi]
- Synthesis and design of a fully integrated multi-topology switched capacitor DC-DC converter with gearbox controlJeppe Gaardsted Davidsen, Yoni Yosef-Hay, Dennis Oland Larsen, Ivan H. H. Jørgensen. 1-6 [doi]
- Zero-crossing detector for a piezoelectric energy harvesterFranz Marcus Schuffny, Michel Hayoz, Cheolyong Bae, Ishan Arya, Madhur Gokhale, Annapragada Hema Chandar, Martin Nielsen-Lonn, Pavel Angelov. 1-6 [doi]
- Mitigating single-event upsets in COTS SDRAM using an EDAC SDRAM controllerEleftherios Kyriakakis, Kalle Ngo, Johnny Öberg. 1-6 [doi]
- Implementation of a fault-tolerant, globally-asynchronous-locally-synchronous, inter-chip NoC communication bridge on FPGAsEleftherios Kyriakakis, Kalle Ngo, Johnny Öberg. 1-6 [doi]
- Can real-time systems benefit from dynamic partial reconfiguration?Luca Pezzarossa, Andreas Toftegaard Kristensen, Martin Schoeberl, Jens Sparsø. 1-6 [doi]