Abstract is missing.
- A 10b 1GS/s Inverter-Based Pipeline ADC in 65nm CMOSTimmy Sundström, Javad Bagheri Asli, Christer Svensson, Atila Alvandpour. 1-4 [doi]
- Exploring Task and Channel Mapping Strategies in Fail-Operational and Hard Real-Time NoCsMax Koenen, Nguyen Anh Vu Doan, Thomas Wild, Andreas Herkersdorf. 1-7 [doi]
- Software-Defined Radio Assessment for Microwave Imaging Breast Cancer DetectionDionisio Carvalho, Alexandre J. Aragão, André Ferrari, Bruno Sanches, Wilhelmus A. M. Van Noije. 1-6 [doi]
- A 500 mV, 4.5 mW, 16 GHz VCO with 33.3% FTR, designed for 5G applicationsPiyush Kumar, Dario Stajic, Enno Böhme, Erkan Nevzat Isa, Linus Maurer. 1-4 [doi]
- Comparative Study of Single, Regular and Flip Well Subthreshold SRAMs in 22 nm FDSOI TechnologySomayeh Hossein Zadeh, Trond Ytterdal, Snorre Aunet. 1-6 [doi]
- HyVE: A Hybrid Voting-based Eviction Policy for CachesAkshay Srivatsa, Sebastian Nagel 0004, Nael Fasfous, Nguyen Anh Vu Doan, Thomas Wild, Andreas Herkersdorf. 1-7 [doi]
- Matrix Decomposition for Massive MIMO DetectionShahriar Shahabuddin, Muhammad Hasibul Islam, Mohammad Shahanewaz Shahabuddin, Mahmoud A. M. Albreem, Markku J. Juntti. 1-6 [doi]
- A FPGA-based Hardware Accelerator for Bayesian Confidence Propagation Neural NetworkLizheng Liu, Deyu Wang, Yuning Wang, Anders Lansner, Ahmed Hemani, Yu Yang, Xiaoming Hu, Zhuo Zou, Lirong Zheng 0001. 1-6 [doi]
- A Parallel and Pipelined Implementation of a Pascal-Simplex Based Two Asset Option Pricer on FPGA using OpenCLAidan O'Mahony, Gil Zeidan, Bernard Hanzon, Emanuel M. Popovici. 1-6 [doi]
- Low Power Class-AB Line Driver with Adaptive Digital Impedance Control for Fast EthernetSimon Buhr, Martin Kreißig, Christian D. Matthus, Florian Protze, Frank Ellinger. 1-7 [doi]
- A Power Efficient, High Gain and High Input Impedance Capacitively-coupled Neural AmplifierErwin H. T. Shad, Tania Moeinfard, Marta Molinas, Trond Ytterdal. 1-5 [doi]
- Multi-threshold Voltage and Dynamic Body Biasing Techniques for Energy Efficient Ultra Low Voltage Subthreshold AddersSomayeh Hossein Zadeh, Trond Ytterdal, Snorre Aunet. 1-6 [doi]
- Digital Timing Error Calibration of Time-Interleaved ADC with Low Sample RateMarko Neitola. 1-7 [doi]
- Novel Lockstep-based Approach with Roll-back and Roll-forward Recovery to Mitigate Radiation-Induced Soft ErrorsServer Kasap, Eduardo Weber Wächter, Xiaojun Zhai, Shoaib Ehsan, Klaus D. McDonald-Maier. 1-7 [doi]
- A 90nm PVT Tolerant Current Mode Frequency Divider with Wide Locking RangeMadhusudan Maiti, Shubhro Chakrabartty, Alaaddin Al-Shidaifat, Hanjung Song, Bidyut K. Bhattacharyya, Alak Majumder. 1-5 [doi]
- Low Power Scheduling of Periodic Hardware Tasks in Flash-Based FPGAsCornelia Wulf, Michael Willig, Diana Göhringer. 1-7 [doi]
- Model-Based Design Space Exploration for Approximate Image Processing on FPGAManu Manuel, Arne Kreddig, Simon Conrady, Nguyen Anh Vu Doan, Walter Stechele. 1-7 [doi]
- A Voltage Controlled Oscillator with Inductive Divider Design and Analysis at Frequencies Above 100 GHzYasir Shafiullah, Rehman Akbar, Mikko Hietanen, Aarno Pärssinen. 1-5 [doi]
- Synthesizable Synchronization FIFOs Utilizing the Asynchronous Pulse-Based Handshake ProtocolAmeer M. S. Abdelhadi. 1-7 [doi]
- A 10-bit 3.75-GS/s Binary-Weighted DAC with 58.6-pJ Energy Consumption in 65-nm CMOSOscar Morales Chacon, J. Jacob Wikner, Atila Alvandpour, Liter Siek. 1-4 [doi]
- Electro-optic Reversible Toffoli Gate with Optimal Count of LiNbO3 Mach-Zehnder InterferometersShashank Awasthi, Saurav Sharma, Sanjeev Kumar Metya, Alak Majumder. 1-7 [doi]
- A Study of the Impact of Formulation of Cost Function in Task Mapping Problem on NoCsJessé Barreto de Barros, Nidhi Anantharajaiah, Mauricio Ayala-Rincón, Carlos Humberto Llanos Quintero, Jürgen Becker 0001. 1-7 [doi]
- Digital Architecture for MUAPs Propagation Speed Estimator triggered by Foot Plant SwitchGiovanni Mezzina, Daniela De Venuto. 1-7 [doi]
- A Low Power Front-end for Biomedical Fluorescence Sensing ApplicationsSeyed Ruhallah Qasemi, Maryam Rafati, Atila Alvandpour. 1-6 [doi]
- Design of a Current Mode Multiplexed Circuit for Integrate & Fire Neuromorphic SystemsVincenzo Bonaiuto, Fausto Sargeni. 1-6 [doi]
- On the Design of a CMOS-integrated Load Modulated Balanced AmplifierTed Johansson, Srivatsa Samji. 1-4 [doi]
- Origins of Intermodulation Distortion in A Pseudo-differential CMOS Beamforming ReceiverNegar Shabanzadeh, Mahmoud Shehab, Rehman Akbar, Aarno Pärssinen, Timo Rahkonen. 1-6 [doi]
- Schmitt Trigger Based Single-Ended Voltage Amplifier with Positive Feedback Control for Ultra-Low-Voltage SuppliesLuis Henrique Rodovalho. 1-6 [doi]
- A Design Method to Minimize the Impact of Bit Conversion Errors in SAR ADCsSiyu Tan, Mattias Palm, Daniele Mastantuono, Roland Strandberg, Lars Sundström, Sven Mattisson, Pietro Andreani. 1-6 [doi]