Abstract is missing.
- 3D technologies for reconfigurable architecturesFabien Clermidy, O. Turkyimaz, Olivier Billoint, Pierre-Emmanuel Gaillardon. 1-2 [doi]
- Exploring alternate trade-offs of placement quality versus runtime in Simulated Annealing algorithmBaqar Raza, Husain Parvez, Muhammad Mohiuddin. 1-5 [doi]
- A reconfigurable distributed architecture for clock generation in large many-core SoCChuan Shan, Dimitri Galayko, Francçis Anceau, Eldar Zianbetov. 1-8 [doi]
- An application scenario for dynamically reconfigurable FPGAsFynn Schwiegelshohn, Michael Hübner. 1-8 [doi]
- Reliably prototyping large SoCs using FPGA clustersPaul J. Fox, A. Theodore Markettos, Simon W. Moore. 1-8 [doi]
- Inexact End-to-End Response Time Analysis as fitness function in search-based task allocation heuristics for hard real-time network-on-chipsYunfeng Ma, M. Norazizi Sham Mohd Sayuti, Leandro Soares Indrusiak. 1-8 [doi]
- A RFID-enabled sensor platform for pervasive monitoringArnaud Vena, Brice Sorli, Alain Foucaran, Yassin Belaizi. 1-4 [doi]
- An evaluation of energy efficient microcontrollersIoanna Tsekoura, Gregor Rebel, Peter Glösekötter, Mladen Berekovic. 1-5 [doi]
- Power efficient Thermally Assisted Switching Magnetic memory based memory systemsSophiane Senni, Lionel Torres, Gilles Sassatelli, Anastasiia Butko, Bruno Mussard. 1-6 [doi]
- General solutions for MTTF and steady-state availability of NMR systemsMoslem Amiri, Vaclav Prenosil. 1-4 [doi]
- SoCRocket - A virtual platform for the European Space Agency's SoC developmentThomas Schuster, Rolf Meyer, Rainer Buchty, Luca Fossati, Mladen Berekovic. 1-7 [doi]
- LatEst: Latency estimation and high speed evaluation for wormhole switched Networks-on-ChipKris Heid, Haoyuan Ying, Christian Hochberger, Klaus Hofmann. 1-7 [doi]
- Reconciling performance and predictability on a many-core through off-line mappingThomas Carle, Manel Djemal, Daniela Genius, François Pêcheux, Dumitru Potop-Butucaru, Robert de Simone, Franck Wajsbürt, Zhen Zhang. 1-8 [doi]
- Sram-Based FPGA proposal for dynamic power management on sensor nodeAlexandre Ingles da Silva, Fabio Dacencio Pereira. 1-7 [doi]
- Fault injection tools based on Virtual MachinesMaha Kooli, Pascal Benoit, Giorgio Di Natale, Lionel Torres, Volkmar Sieh. 1-6 [doi]
- Design-space exploration between FPGA and ASIFMuhammad Amin Qureshi, Husain Parvez. 1-5 [doi]
- A coding-based configurable and asymmetrical redundancy scheme for 3-D interconnectsChristof Osewold, Wolfgang Buter, Alberto García Ortiz. 1-8 [doi]
- A hierarchical reconfigurable micro-coded multi-core processor for IoT applicationsNing Ma, Zhuo Zou, Zhonghai Lu, Li-Rong Zheng, Stefan Blixt. 1-4 [doi]
- Incremental checkpointing of program state to NVRAM for transiently-powered systemsFaycal Ait Aouda, Kevin Marquet, Guillaume Salagnac. 1-4 [doi]
- New paradigms for access control in constrained environmentsA. Cherkaoui, L. Bossuet, Ludwig Seitz, Göran Selander, R. Borgaonkar. 1-4 [doi]
- A review on wireless sensor node architecturesF. Karray, M. W. Jmal, Mohamed Abid, Mohammed S. BenSaleh, Abdulfattah Mohammad Obeid. 1-8 [doi]
- Feedback-based admission control for task allocationPiotr Dziurzanski, Hashem Ali Ghazzawi, Leandro Soares Indrusiak. 1-5 [doi]
- Low overhead predictability enhancement in non-preemptive network-on-chip routers using Priority Forwarded Packet SplittingBharath Sudev, Leandro Soares Indrusiak. 1-8 [doi]
- A prototyping platform for virtual reconfigurable unitsLoïc Lagadec, Jean-Christophe Le Lann, Theotime Bollengier. 1-7 [doi]
- Novel configurable logic block architecture exploiting controllable-polarity transistorsPierre-Emmanuel Gaillardon, Xifan Tang, Giovanni De Micheli. 1-3 [doi]
- Dynamic management of multikernel multithread accelerators using Dynamic Partial ReconfigurationAlfonso Rodriguez, Juan Valverde, Eduardo de la Torre, Teresa Riesgo. 1-7 [doi]
- Reconfigurable Bus Monitor Tool Suite for on-chip SoC for performance and protocol monitoringPing-Chun Lee, Ing-Jer Huang. 1-6 [doi]
- Using JSON to manage communication between services in the Internet of ThingsPhilipp Wehner, Christina Piberger, Diana Göhringer. 1-4 [doi]
- MRAPI resource management layer on reconfigurable systems-on-chipLaurent Gantel, Mohamed El Amine Benkhelifa, François Verdier, Fabrice Lemonnier. 1-7 [doi]
- Leveraging partial dynamic reconfiguration on Zynq SoC FPGAsJaime Correa Rodriguez, Kurt Franz Ackermann. 1-6 [doi]
- Interrupt aware queue implementation for energy efficient multitasking systems based on Cortex-M3 architectureGregor Rebel, Francisco J. Estevez, Ioanna Tsekoura, Ingo Schulz, Peter Glösekötter. 1-7 [doi]
- A hardware/software co-design reconfigurable Network-on-Chip FPGA emulation methodHaoyuan Ying, Thomas Hollstein, Klaus Hofmann. 1-8 [doi]
- Communication-centric design for FMC based I/O systemMokhtar Bouain, Venkatasubramanian Viswanathan, Rabie Ben Atitallah, Jean-Luc Dekeyser. 1-8 [doi]
- Emerging Non-Volatile Memory technologies for future low power reconfigurable systemsAli Ahari, Hossein Asadi, Mehdi Baradaran Tahoori. 1-2 [doi]
- Non-intrusive DVFS emulation in gem5 with application to self-aware architecturesParham Haririan, Alberto García Ortiz. 1-7 [doi]
- Multi-shape tasks scheduling for online multitasking on FPGAsGuy Wassi, Mohamed El Amine Benkhelifa, Geoff Lawday, François Verdier, Samuel Garcia. 1-7 [doi]
- A reconfigurable optical network on chip for streaming applicationsSébastien Le Beux, Hui Li, Gabriela Nicolescu, Ian O'Connor. 1-2 [doi]
- HNCP-II: A 16-core 65nm microprocessor ASIC for image processing algorithmsMohamed Amine Boussadi, Thierry Tixier, Alexis Landrault, Jean-Pierre Dérutin. 1-7 [doi]