Abstract is missing.
- Design method for asymmetric 3D interconnect architectures with high level modelsJan Moritz Joseph, Lennart Bamberg, Sven Wrieden, Dominik Ermel, Alberto Garcia-Oritz, Thilo Pionteck. 1-8 [doi]
- High-level design using Intel FPGA OpenCL: A hyperspectral imaging spatial-spectral classifierR. Domingo, Rubén Salvador, Himar Fabelo, Daniel Madroñal, Samuel Ortega, Raquel Lazcano, Eduardo Juárez, Gustavo Marrero Callicó, César Sanz. 1-8 [doi]
- Adaptive and reconfigurable bubble routing technique for 2D Torus interconnection networksPoona Bahrebar, Dirk Stroobandt. 1-8 [doi]
- Programmable SoC platform for deep packet inspection using enhanced Boyer-Moore algorithmAdrián Dominguez, Pedro P. Carballo, Antonio Núñez. 1-8 [doi]
- On-demand instantiation of co-processors on dynamically reconfigurable FPGAsMarcel Essig, Kurt Franz Ackermann. 1-8 [doi]
- High-level test generation for processing elements in many-core systemsStephen Adeboye Oyeniran, Raimund Ubar, Siavoosh Payandeh Azad, Jaan Raik. 1-8 [doi]
- Characterization and optimization of behavioral hardware accelerators in heterogeneous MPSoCsYidi Liu, Monica Villaverde, Félix Moreno, Benjamin Carrión Schäfer. 1-8 [doi]
- SecBoot - lightweight secure boot mechanism for Linux-based embedded systems on FPGAsPeter Rouget, Benoît Badrignans, Pascal Benoit, Lionel Torres. 1-5 [doi]
- Analysis of a heterogeneous multi-core, multi-hw-accelerator-based system designed using PREESM and SDSoCLeonardo Suriano, Alfonso Rodriguez, Karol Desnos, Maxime Pelcat, Eduardo de la Torre. 1-7 [doi]
- Design and scalability analysis of bandwidth-compressed stream computing with multiple FPGAsAntoniette Mondigo, Tomohiro Ueno, Daichi Tanaka, Kentaro Sano, Satoru Yamamoto. 1-8 [doi]
- Exploring the performance of partially reconfigurable point-to-point interconnectsEl Mehdi Abdali, Maxime Pelcat, François Berry, Jean-Philippe Diguet, Francesca Palumbo. 1-6 [doi]
- Side-channel attack resilience through route randomisation in secure real-time Networks-on-ChipLeandro Soares Indrusiak, James Harbin, Martha Johanna Sepúlveda. 1-8 [doi]
- Towards trace-driven cache attacks on Systems-on-Chips - exploiting bus communicationJohanna Sepúlveda, Mathieu Gross, Andreas Zankl, Georg Sigl. 1-7 [doi]
- ElasticSimMATE: A fast and accurate gem5 trace-driven simulator for multicore systemsAlejandro Nocua, Florent Bruguier, Gilles Sassatelli, Abdoulaye Gamatié. 1-8 [doi]
- Fault-resilient NoC router with transparent resource allocationTsotne Putkaradze, Siavoosh Payandeh Azad, Behrad Niazmand, Jaan Raik, Gert Jervan. 1-8 [doi]
- Fault recovery and adaptation in time-triggered Networks-on-Chips for mixed-criticality systemsHamidreza Ahmadian, Farzad Nekouei, Roman Obermaisser. 1-8 [doi]
- Energy aware and reliable STT-RAM based cache design for 3D embedded chip-multiprocessorsFatemeh Arezoomand, Arghavan Asad, Mahdi Fazeli, Mahmood Fathy, Farah Mohammadi. 1-8 [doi]
- Computational self-awareness as design approach for visual sensor nodesZakarya Guettatfi, Philipp Hubner, Marco Platzner, Bernhard Rinner. 1-8 [doi]
- Current mode detection in hard real-time automotive applications dedicated to many-core platformsPiotr Dziurzanski, Tomasz Maka. 1-8 [doi]
- System-level design for communication-centric task farm applicationsDaniela Genius, Ludovic Apvrille. 1-8 [doi]
- Federated system-to-service authentication and authorization combining PUFs and tokensMarta Beltrán, Miguel Calvo, Sergio Gonzalez. 1-8 [doi]