Abstract is missing.
- Applying Data Mapping Techniques to Vector DSPsPeter Westermann, Ludwig Schwoerer, Andre Kaufmann. 1-8 [doi]
- Instruction Set Encoding Optimization for Code Size ReductionMichael Med, Andreas Krall. 9-17 [doi]
- FlexCore: Utilizing Exposed Datapath Control for Efficient ComputingMartin Thuresson, Magnus Själander, Magnus Björk, Lars J. Svensson, Per Larsson-Edefors, Per Stenström. 18-25 [doi]
- Prototyping Efficient Interprocessor Communication MechanismsVassilis Papaefstathiou, Dionisios N. Pnevmatikatos, Manolis Marazakis, Giorgos Kalokairinos, Aggelos Ioannou, Michael Papamichael, Stamatis Kavadias, Giorgos Mihelogiannakis, Manolis Katevenis. 26-33 [doi]
- Design Space Exploration of Configuration Manager for Network Processing ApplicationsChristoforos Kachris, Stamatis Vassiliadis. 34-40 [doi]
- Design Space Exploration of Media Processors: A Parameterized SchedulerGuillermo Payá Vayá, Javier Martín-Langerwerf, Piriya Taptimthong, Peter Pirsch. 41-49 [doi]
- Automatic Bus Matrix Synthesis based on Hardware Interface Selection for Fast Communication Design Space ExplorationGanghee Lee, Seokhyun Lee, Yongjin Ahn, Kiyoung Choi. 50-57 [doi]
- Systematic Data Structure Exploration of Multimedia and Network Applications realized Embedded SystemsLazaros Papadopoulos, Christos Baloukas, Nikolaos Zompakis, Dimitrios Soudris. 58-65 [doi]
- On the Problem of Minimizing Workload Execution Time in SMT ProcessorsFrancisco J. Cazorla, Enrique Fernández, Peter M. W. Knijnenburg, Alex Ramírez, Rizos Sakellariou, Mateo Valero. 66-73 [doi]
- Performance and Power Analysis of Parallelized Implementations on an MPCore Multiprocessor PlatformHolger Blume, Jörg von Livonius, Lisa Rotenberg, Tobias G. Noll, Harald Bothe, Jörg Brakensiek. 74-81 [doi]
- An Interrupt Controller for FPGA-based MultiprocessorsAntonino Tumeo, Marco Branca, Lorenzo Camerini, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto. 82-87 [doi]
- Application Case Studies on HS-Scale, a MP-SOC for Embbeded SystemsNicolas Saint-Jean, Pascal Benoit, Gilles Sassatelli, Lionel Torres, Michel Robert. 88-95 [doi]
- A Hardware/Software Architecture for Tool Path Computation. An Application to Turning Lathe MachiningSergio A. Cuenca, Antonio Martinez, Antonio Jimeno, José Luis Sánchez. 96-102 [doi]
- Energy efficiency of mobile video decodingTero Rintaluoma, Olli Silvén. 103-109 [doi]
- Instruction-Level Fault Tolerance ConfigurabilityDemid Borodin, Ben H. H. Juurlink, Stamatis Vassiliadis. 110-117 [doi]
- The Weight-Watcher Service and its Lightweight ImplementationBenoît Garbinato, Rachid Guerraoui, Jarle Hulaas, Alexei Kounine, Maxime Monod, Jesper Honig Spring. 118-127 [doi]
- COSMOS: A System-Level Modelling and Simulation Framework for Coprocessor-Coupled Reconfigurable SystemsKehuai Wu, Jan Madsen. 128-136 [doi]
- Flexibility Inlining into Arithmetic Data-paths Exploiting A Regular Interconnection SchemeSotirios Xydis, George Economakos, Kiamal Z. Pekmestzi. 137-144 [doi]
- An Evolutionary Approach to Area-Time Optimization of FPGA designsFabrizio Ferrandi, Pier Luca Lanzi, Gianluca Palermo, Christian Pilato, Donatella Sciuto, Antonino Tumeo. 145-152 [doi]
- The ARISE Reconfigurable Instruction Set Extensions FrameworkNikolaos Vassiliadis, George Theodoridis, Spiridon Nikolaidis. 153-160 [doi]
- Simulative Buffer Analysis of Local Image Processing Algorithms Described by Windowed Synchronous Data FlowJoachim Keinert, Christian Haubelt, Jürgen Teich. 161-168 [doi]
- Online Prediction of Applications Cache UtilityMiquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero. 169-177 [doi]
- Maximum and Sorted Cache Occupation Using Array PaddingEzequiel Herruzo, Emilio L. Zapata, Oscar G. Plata. 178-185 [doi]
- A Memory-Efficient Reconfigurable Aho-Corasick FSM Implementation for Intrusion Detection SystemsVassilis Dimopoulos, Ioannis Papaefstathiou, Dionisios N. Pnevmatikatos. 186-193 [doi]
- A Side-channel Attack Resistant Programmable PKC Coprocessor for Embedded ApplicationsNele Mentens, Kazuo Sakiyama, Lejla Batina, Bart Preneel, Ingrid Verbauwhede. 194-200 [doi]
- Secure and Authenticated Communication in Chip-Level Microcomputer Bus Systems with Tree Parity MachinesSascha Mühlbach, Sebastian Wallner. 201-208 [doi]
- A Simulation-Based Methodology for Evaluating the DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML TechnologiesFrancesco Regazzoni, Stéphane Badel, Thomas Eisenbarth, Johann Großschädl, Axel Poschmann, Zeynep Toprak Deniz, Marco Macchetti, Laura Pozzi, Christof Paar, Yusuf Leblebici, Paolo Ienne. 209-214 [doi]