Table of Contents

• Maximum performance computing for exascale applicationsOskar Mencer. [doi]
• PrefaceJohn McAllister, Shuvra Bhattacharyya. [doi]
• The homogeneity of architecture in a heterogeneous worldJohn Goodacre. [doi]
• It's about timeEdward A. Lee. [doi]
• Just-in-Time Verification in ADL-based processor designDominik Auras, Andreas Minwegen, Uwe Deidersen. 1-6 [doi]
• Interleaving methods for hybrid system-level MPSoC design space explorationRoberta Piscitelli, Andy D. Pimentel. 7-14 [doi]
• A template-based methodology for efficient microprocessor and FPGA accelerator co-designAngeliki Kritikakou, Francky Catthoor, George Athanasiou, Vasilios I. Kelefouras, Costas E. Goutis. 15-22 [doi]
• Using OpenMP superscalar for parallelization of embedded and consumer applicationsMichael Andersch, Chi Ching Chi, Ben H. H. Juurlink. 23-32 [doi]
• Virtual prototyping for efficient multi-core ECU development of driver assistance systemsRainer Kiesel, Martin Streubühr, Christian Haubelt, Anestis Terzis, Jürgen Teich. 33-40 [doi]
• System modeling and multicore simulation using transactionsAmine Anane, El Mostapha Aboulhamid, Yvon Savaria. 41-50 [doi]
• HNOCS: Modular open-source simulator for Heterogeneous NoCsYaniv Ben-Itzhak, Eitan Zahavi, Israel Cidon, Avinoam Kolodny. 51-57 [doi]
• BADCO: Behavioral Application-Dependent Superscalar Core modelRicardo Velasquez, Pierre Michaud, André Seznec. 58-67 [doi]
• An application-specific Network-on-Chip for control architectures in RF transceiversSiegfried Brandstätter, Mario Huemer. 68-75 [doi]
• A framework for efficient cache resizingGeorgios Keramidas, Chrysovalantis Datsios, Stefanos Kaxiras. 76-85 [doi]
• OSR-Lite: Fast and deadlock-free NoC reconfiguration frameworkAlessandro Strano, Davide Bertozzi, Francisco Triviño, José L. Sánchez, Francisco J. Alfaro, Jose Flich. 86-95 [doi]
• A tightly-coupled multi-core cluster with shared-memory HW acceleratorsMasoud Dehyadegari, Andrea Marongiu, Mohammad Reza Kakoee, Luca Benini, Siamak Mohammadi, Naser Yazdani. 96-103 [doi]
• Architecture-level fault-tolerance for biomedical implantsRobert M. Seepers, Christos Strydis, Georgi Nedeltchev Gaydadjiev. 104-112 [doi]
• Reconfigurable miniature sensor nodes for condition monitoringTeemu Nylanden, Jani Boutellier, Karri Nikunen, Jari Hannuksela, Olli Silvén. 113-119 [doi]
• Counting stream registers: An efficient and effective snoop filter architectureAanjhan Ranganathan, Ali Galip Bayrak, Theo Kluter, Philip Brisk, Edoardo Charbon, Paolo Ienne. 120-127 [doi]
• Design space exploration in application-specific hardware synthesis for multiple communicating nested loopsRosilde Corvino, Abdoulaye Gamatié, Marc Geilen, Lech Józwiak. 128-135 [doi]
• Automatic FPGA synthesis of memory intensive C-based kernelsMatthew Milford, John McAllister. 136-143 [doi]
• Throughput driven transformations of Synchronous Data Flows for mapping to heterogeneous MPSoCsAnastasia Stulova, Rainer Leupers, Gerd Ascheid. 144-151 [doi]
• K-Periodic schedules for evaluating the maximum throughput of a Synchronous Dataflow graphBruno Bodin, Alix Munier Kordon, Benoît Dupont de Dinechin. 152-159 [doi]
• Memory bounds for the distributed execution of a hierarchical Synchronous Data-Flow graphKarol Desnos, Maxime Pelcat, Jean-François Nezan, Slaheddine Aridhi. 160-167 [doi]
• Out-Of-order execution of synchronous data-flow networksDaniel Baudisch, Jens Brandt, Klaus Schneider. 168-175 [doi]
• An efficient asymmetric distributed lock for embedded multiprocessor systemsJochem H. Rutgers, Marco Jan Gerrit Bekooij, Gerard J. M. Smit. 176-182 [doi]
• Simultaneous reconfiguration of issue-width and instruction cache for a VLIW processorFakhar Anjam, Stephan Wong, Luigi Carro, Gabriel L. Nazar, Mateus B. Rutzig. 183-192 [doi]
• Energy efficient stream-based configurable architecture for embedded platformsFrederico Pratas, Pedro Tomás, Pedro Trancoso, Leonel Sousa. 193-200 [doi]
• TaBit: A framework for task graph to bitstream generationAlessandra Bonetto, Andrea Cazzaniga, Gianluca Durelli, Christian Pilato, Donatella Sciuto, Marco D. Santambrogio. 201-208 [doi]
• System-on-Chip deployment with MCAPI abstraction and IP-XACT metadataLauri Matilainen, Lasse Lehtonen, Joni-Matti Määttä, Erno Salminen, Timo D. Hämäläinen. 209-216 [doi]
• Efficient system design using the Statistical Analysis of Architectural Bottlenecks methodologyManish Arora, Feng Wang, Bob Rychlik, M. Tullsen. 217-226 [doi]
• Special session on "programming paradigms for reconfigurable multi-core embedded systems"Diana Göhringer, Pedro C. Diniz. 227 [doi]
• Towards future adaptive multiprocessor systems-on-chip: An innovative approach for flexible architecturesFabrice Lemonnier, Philippe Millet, Gabriel Marchesan Almeida, Michael Hübner, Jürgen Becker, Sébastien Pillement, Olivier Sentieys, Martijn Koedam, Shubhendu Sinha, Kees Goossens, Christian Piguet, Marc-Nicolas Morgan, Romain Lemaire. 228-235 [doi]
• Adaptive reinforcement learning method for networks-on-chipFahimeh Farahnakian, Masoumeh Ebrahimi, Masoud Daneshtalab, Juha Plosila, Pasi Liljeberg. 236-243 [doi]
• Adaptive processor architecture - invited paperMichael Hübner, Diana Göhringer, Carsten Tradowsky, Jörg Henkel, Jürgen Becker. 244-251 [doi]
• Adaptive dynamic memory allocators by estimating application workloadsIoannis Koutras, Alexandros Bartzas, Dimitrios Soudris. 252-259 [doi]
• Hardware/software specialization through aspects: The LARA approachJoão M. P. Cardoso, Tiago Carvalho, João Teixeira, Pedro C. Diniz, Fernando M. Gonçalves, Zlatko Petrov. 260-267 [doi]
• From Scilab to multicore embedded systems: Algorithms and methodologiesGeorge Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Christos Valouxis, Christos Gogos, Nikolaos Kavvadias, Grigoris Dimitroulakos, Kostas Masselos, Diana Göhringer, Steven Derrien, Daniel Menard, Olivier Sentieys, Michael Hübner, Timo Stripf, Oliver Oey, Jürgen Becker, Gerard K. Rauwerda, Kim Sunesen, Dimitrios Kritharidis, Nikolaos Mitas. 268-275 [doi]
• Special session on "FPGA-based emulation of hardware architectures"Holger Blume. 276 [doi]
• BEE technology overviewJoseph Rothman, Chen Chang. 277 [doi]
• An FPGA-accelerated testbed for hardware component development in MIMO wireless communication systemsFilippo Borlenghi, Dominik Auras, Ernst Martin Witte, Torsten Kempf, Gerd Ascheid, Rainer Leupers, Heinrich Meyr. 278-285 [doi]
• An FPGA-based prototyping method for verification, characterization and optimization of LDPC error correction systemsPanagiotis Sakellariou, I. Tsatsaragkos, Nikos Kanistras, Ahmed Mahdi, Vassilis Paliouras. 286-293 [doi]
• A quantitative analysis of fixed-point LDPC-decoder implementations using hardware-accelerated HDL emulationsMatthias Korb, Tobias G. Noll. 294-301 [doi]
• An FPGA-based probability-aware fault simulatorDavid May, Walter Stechele. 302-309 [doi]
• Combining on-hardware prototyping and high-level simulation for DSE of multi-ASIP systemsPaolo Meloni, Sebastiano Pomata, Luigi Raffo, Roberta Piscitelli, Andy D. Pimentel. 310-317 [doi]
• Special session on "aspects of Cyber-Physical Systems"Ed F. Deprettere. 318 [doi]
• Rigorous design of cyber-physical systemsJoseph Sifakis. 319 [doi]
• Predictable dynamic embedded data processingMarc Geilen, Sander Stuijk, Twan Basten. 320-327 [doi]
• Efficient computing in cyber-physical systemsPeter Marwedel, Michael Engel. 328-332 [doi]
• Is time predictability quantifiable?Martin Schoeberl. 333-338 [doi]
• Model-driven robot-software design using integrated models and co-simulationJan F. Broenink, Yunyun Ni. 339-344 [doi]
• Multicore enablement for Cyber Physical SystemsAndreas Herkersdorf. 345 [doi]
• Challenges in automotive cyber-physical systems designDip Goswami, Reinhard Schneider 0001, Alejandro Masrur, Martin Lukasiewycz, Samarjit Chakraborty, Harald Voit, Anuradha Annaswamy. 346-354 [doi]
• A co-simulation approach for system-level analysis of embedded control systemsMichael Glaß, Jürgen Teich, Liyuan Zhang. 355-362 [doi]
• Instrumentation techniques for cyber-physical systems using the targeted dataflow interchange formatShuvra S. Bhattacharyya. 363 [doi]
• Efficient hardware implementation of data-flow parallel embedded systemsPatrice Quinton, Anne-Marie Chana, Steven Derrien. 364-371 [doi]