Table of Contents

• The Heterogeneous System Architecture: It's beyond the GPUPaul Blinzer. [doi]
• Scaling usable computing capabilityTor M. Aamodt. [doi]
• High-bandwidth, high-capacity, low-power memory systemsBruce Jacob. [doi]
• Co-design of many-accelerator heterogeneous systems exploiting virtual platformsEfstathios Sotiriou-Xanthopoulos, Sotirios Xydis, Kostas Siozios, George Economakos. 1-8 [doi]
• PrefaceCarlo Galuzzi, Alexander V. Veidenbaum. 1 [doi]
• Robustness analysis of multiprocessor schedulesShreya Adyanthaya, Zhihui Zhang, Marc Geilen, Jeroen Voeten, Twan Basten, Ramon R. H. Schiffelers. 9-17 [doi]
• Dynamic-vector execution on a general purpose EDGE chip multiprocessorMilovan Duric, Oscar Palomar, Aaron Smith, Milan Stanic, Osman S. Unsal, Adrián Cristal, Mateo Valero, Doug Burger, Alexander V. Veidenbaum. 18-25 [doi]
• Combining application adaptivity and system-wide Resource Management on multi-core platformsGiuseppe Massari, Edoardo Paone, Patrick Bellasi, Gianluca Palermo, Vittorio Zaccaria, William Fornaciari, Cristina Silvano. 26-33 [doi]
• Resource conscious prefetching for irregular applications in multicoresMuneeb Khan, Erik Hagersten. 34-43 [doi]
• Characterizing communication behavior of dataflow programs using trace analysisJörn W. Janneck, Simone Casale Brunet, Marco Mattavelli. 44-50 [doi]
• On tokens and signals: Bridging the semantic gap between dataflow models and hardware implementationsStavros Tripakis, Rhishikesh Limaye, Kaushik Ravindran, Guoqiang Wang. 51-58 [doi]
• Automated design flow for coarse-grained reconfigurable platforms: An RVC-CAL multi-standard decoder use-caseCarlo Sau, Luigi Raffo, Francesca Palumbo, Endri Bezati, Simone Casale Brunet, Marco Mattavelli. 59-66 [doi]
• WCET-aware scheduling optimizations for multi-core real-time systemsTimon Kelter, Hendrik Borghorst, Peter Marwedel. 67-74 [doi]
• A run-time modulo scheduling by using a binary translation mechanismRicardo S. Ferreira, Waldir Denver, Monica Magalhães Pereira, Jorge Quadros, Luigi Carro, Stephan Wong. 75-82 [doi]
• Evaluating the memory system behavior of smartphone workloadsG. Narancic, P. Judd, D. Wu, Islam Atta, M. Elnacouzi, Jason Zebchuk, J. Albericio, Natalie D. Enright Jerger, Andreas Moshovos, K. Kutulakos, S. Gadelrab. 83-92 [doi]
• Memory sharing techniques for multi-standard high-throughput FEC decoderZhenzhi Wu, Dake Liu. 93-98 [doi]
• Speculative synchronization for coherence-free embedded NUMA architecturesDimitra Papagiannopoulou, Tali Moreshet, Andrea Marongiu, Luca Benini, Maurice Herlihy, R. Iris Bahar. 99-106 [doi]
• Extended performance analysis of the time predictable on-demand coherent data cache for multi- and many-core systemsArthur Pyka, Mathias Rohde, Sascha Uhrig. 107-114 [doi]
• GPGPU workload characteristics and performance analysisSohan Lal, Jan Lucas, Michael Andersch, Mauricio Alvarez Mesa, Ahmed Elhossini, Ben H. H. Juurlink. 115-124 [doi]
• Performance evaluation of the Intel Xeon Phi manycore architecture using parallel video-based driver assistance algorithmsOliver Jakob Arndt, Daniel Becker, Florian Giesemann, Guillermo Payá Vayá, Christopher Bartels, Holger Blume. 125-132 [doi]
• Pre-architectural performance estimation for ASIP design based on abstract processor modelsJuan Fernando Eusse Giraldo, Christopher Williams, Luis Gabriel Murillo, Rainer Leupers, Gerd Ascheid. 133-140 [doi]
• Design space exploration for fair resource-allocated NoC architecturesAntonis Psathakis, Vassilis Papaefstathiou, Manolis Katevenis, Dionisios N. Pnevmatikatos. 141-148 [doi]
• Variable length instruction compression on Transport Triggered ArchitecturesJanne Helkala, Timo Viitanen, Heikki Kultala, Pekka Jääskeläinen, Jarmo Takala, Tommi Zetterman, Heikki Berg. 149-155 [doi]
• Fast Dynamic Binary Rewriting for flexible thread migration on shared-ISA heterogeneous MPSoCsGiorgis Georgakoudis, Dimitrios S. Nikolopoulos, Hans Vandierendonck, Spyros Lalis. 156-163 [doi]
• MPSoCBench: A toolset for MPSoC system level evaluationLiana Duenha, Marcelo Guedes, Henrique Almeida, Matheus Boy, Rodolfo Azevedo. 164-171 [doi]
• Modeling the temperature bias of power consumption for nanometer-scale CPUs in application processorsKarel De Vogeleer, Gérard Memmi, Pierre Jouvelot, Fabien Coelho. 172-180 [doi]
• An ESL timing & power estimation and simulation framework for heterogeneous socsKim Grüttner, Philipp A. Hartmann, Tiemo Fandrey, Kai Hylla, Daniel Lorenz, Stefan Stattelmann, Björn Sander, Oliver Bringmann, Wolfgang Nebel, Wolfgang Rosenstiel. 181-190 [doi]
• Evaluating private vs. shared last-level caches for energy efficiency in asymmetric multi-coresAnthony Gutierrez, Ronald G. Dreslinski, Trevor N. Mudge. 191-198 [doi]
• Software-controlled processor stalls for time and energy efficient data locality optimizationPhilippe Clauss, Imen Fassi, Alexandra Jimborean. 199-206 [doi]
• Multi-FPGA prototyping board issue: the FPGA I/O bottleneckQingshan Tang, Habib Mehrez, Matthieu Tuna. 207-214 [doi]
• Synthesis of Instruction Extensions on HyperCell, a reconfigurable datapathKavitha T. Madhu, Saptarsi Das, Madhava Krishna C, Nalesh S, S. K. Nandy, Ranjani Narayan. 215-224 [doi]
• Co-exploration of NLA kernels and specification of Compute Elements in distributed memory CGRAsMahesh Mahadurkar, Farhad Merchant, Arka Maity, Kapil Vatwani, Ishan Munje, Nandhini Gopalan, S. K. Nandy, Ranjani Narayan. 225-232 [doi]
• RuRot: Run-time rotatable-expandable partitions for efficient mapping in CGRAsSyed M. A. H. Jafri, Guilermo Serrano, Junaid Iqbal, Masoud Daneshtalab, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen. 233-241 [doi]
• Asynchronous parallel simulation with transaction eventsBastian Haetzer, Martin Radetzki. 242-249 [doi]
• Highly-parallel special-purpose multicore architecture for SystemC/TLM simulationsNicolas Ventroux, Julien Peeters, Tanguy Sassolas, James C. Hoe. 250-257 [doi]
• Architectural low-power design using transaction-based system modeling and simulationFabian Mischkalla, Wolfgang Mueller. 258-265 [doi]
• Micro-architectural simulation of in-order and out-of-order ARM microprocessors with gem5Fernando A. Endo, Damien Couroussé, Henri-Pierre Charles. 266-273 [doi]
• Ranking software components using a modified PageRank algorithm including safety aspectsDominik Reinhardt. 274-281 [doi]
• Evaluation of message passing synchronization algorithms in embedded systemsLazaros Papadopoulos, Ivan Walulya, Philippas Tsigas, Dimitrios Soudris, Brendan Barry. 282-289 [doi]
• Efficient end-to-end latency distribution analysis for probabilistic time-triggered systemsMark Westmijze, Marco Jan Gerrit Bekooij, Gerard J. M. Smit. 290-298 [doi]
• An automotive specific MILP model targeting power-aware function partitioningGregor Walla, Andreas Herkersdorf, Andre S. Enger, Andreas Barthels, Hans-Ulrich Michel. 299-306 [doi]
• The DESERVE project: Towards future ADAS functionsMatti Kutila, Pasi Pyykonen, Paul van Koningsbruggen, Nereo Pallaro, Joshué Pérez Rastelli. 308-313 [doi]
• A comprehensive ASIC/FPGA prototyping environment for exploring embedded processing systems for advanced driver assistance applicationsFlorian Giesemann, Guillermo Payá Vayá, Holger Blume, Matthias Limmer, Werner Ritter. 314-321 [doi]
• Development and design of a platform for arbitration and sharing control applicationsJoshué Pérez, David Gonzalez, Fawzi Nashashibi, Gwenaël Dunand, Fabio Tango, Nereo Pallaro, Andre Rolfsmeier. 322-328 [doi]
• Vehicle-Hardware-In-The-Loop system for ADAS prototyping and validationClement Galko, Romain Rossi, Xavier Savatier. 329-334 [doi]
• Instruction-set extension for an ASIP-based SIFT feature extractionNico Mentzer, Guillermo Payá Vayá, Holger Blume, Nora von Egloffstein, Werner Ritter. 335-342 [doi]
• Definition of an embedded driver model for driving behavior prediction within the DESERVE platformJens Klimke, Philipp Themann, Christoph Klas, Lutz Eckstein. 343-350 [doi]
• Massively parallel signal processing challenges within a driver assistant prototype framework first case study results with a novel MIMO-radarFrank Meinl, Martin Kunert, Holger Blume. 351-357 [doi]
• Neuronal connectivity assessment for epileptic seizure prevention: Parallelizing the generalized partial directed coherence on many-core platformsGeorgios Georgis, Dionysios I. Reisis, Panagiotis Skordilakis, Konstantinos S. Tsakalis, Ashfaque Bin Shafique, George Chatzikonstantis, George Lentaris. 359-366 [doi]
• Optimal mapping of inferior olive neuron simulations on the Single-Chip Cloud ComputerDimitrios Rodopoulos, Giorgos Chatzikonstantis, Andreas Pantelopoulos, Dimitrios Soudris, Chris I. De Zeeuw, Christos Strydis. 367-374 [doi]
• An analysis of dynamics of CA3b in HippocampusB. Keshavarz Hedayati, Nikitas J. Dimopoulos, A. Babul. 375-383 [doi]