Abstract is missing.
- Exploring different execution paradigms in exposed datapath architectures with buffered processing unitsAnoop Bhagyanath, Klaus Schneider 0001. 1-10 [doi]
- RACOS: Transparent access and virtualization of reconfigurable hardware acceleratorsCharalampos Vatsolakis, Dionisios N. Pnevmatikatos. 11-19 [doi]
- System on chip generation for multi-sensor and sensor fusion applicationsTobias Lieske, Benjamin Pfundt, Steffen Vaas, Marc Reichenbach, Dietmar Fey. 20-29 [doi]
- An event-based Network-on-Chip debugging system for FPGA-based MPSoCsHabib ul Hasan Khan, Jens Rettkowski, Mohamed Eldafrawy, Diana Göhringer. 30-37 [doi]
- SysRT: A modular multiprocessor RTOS simulator for early design space explorationJun Xiao, Andy D. Pimentel, Giuseppe Lipari. 38-45 [doi]
- Network/system co-simulation for design space exploration of IoT applicationsZhuoran Zhao, Vasileios Tsoutsouras, Dimitrios Soudris, Andreas Gerstlauer. 46-53 [doi]
- A generic processing in memory cycle accurate simulator under hybrid memory cube architectureGeraldo F. Oliveira, Paulo C. Santos, Marco Antonio Zanata Alves, Luigi Carro. 54-61 [doi]
- System simulation with gem5 and SystemC: The keystone for full interoperabilityChristian Menard, Jerónimo Castrillón, Matthias Jung 0001, Norbert Wehn. 62-69 [doi]
- SPynq: Acceleration of machine learning applications over Spark on PynqChristoforos Kachris, Elias Koromilas, Ioannis Stamelos, Dimitrios Soudris. 70-77 [doi]
- Balanced application-specific processor system for efficient SIFT-feature detectionJulian Hartig, Guillermo Payá Vayá, Nico Mentzer, Holger Blume. 78-87 [doi]
- Analyzing the trade-off between power consumption and beamforming algorithm performance using a hearing aid ASIPLukas Gerlach, Guillermo Payá Vayá, Shuang Liu, Moritz Weisbrich, Holger Blume, Daniel Marquardt, Simon Doclo. 88-96 [doi]
- Can a reconfigurable architecture beat ASIC as a CNN accelerator?Syed M. A. H. Jafri, Ahmed Hemani, Dimmitrios Stathis. 97-104 [doi]
- Adaptive runtime exploiting sparsity in tensor of deep learning neural network on heterogeneous systemsKuo-You Peng, Sheng-Yu Fu, Yu-Ping Liu, Wei-Chung Hsu. 105-112 [doi]
- Neuromorphic self-organizing map design for classification of bioelectric-timescale signalsJohan Mes, Ester Stienstra, Xuefei You, Sumeet S. Kumar, Amir Zjajo, Carlo Galuzzi, Rene van Leuken. 113-120 [doi]
- Evaluation of fine-grained parallelism in AUTOSAR applicationsAlexander Stegmeier, Sebastian Kehr, Dave George, Christian Bradatsch, Milos Panic, Bert Bodekker, Theo Ungerer. 121-128 [doi]
- FPGA-based evaluation platform for disaggregated computingDimitris Theodoropoulos, Nikolaos Alachiotis, Dionisios N. Pnevmatikatos. 129-136 [doi]
- Towards real-time whisker tracking in rodents for studying sensorimotor disordersYang Ma, Prajith Ramakrishnan Geethakumari, Georgios Smaragdos, Sander Lindeman, Vincenzo Romano, Mario Negrello, Ioannis Sourdis, Laurens W. J. Bosman, Chris I. De Zeeuw, Zaid Al-Ars, Christos Strydis. 137-145 [doi]
- Algorithmic and memory optimizations on multiple application mapping onto FPGAsHarry Sidiropoulos, Ioannis Koutras, Dimitrios Soudris, Kostas Siozios. 146-153 [doi]
- Extraction of recursion level parallelism for embedded multicore systemsMiguel Angel Aguilar, Rainer Leupers, Gerd Ascheid, Juan Fernando Eusse. 154-162 [doi]
- Dynamic function specializationA. P. Arif Ali, Erven Rohou. 163-170 [doi]
- Exposed datapath optimizations for loop schedulingHeikki O. Kultala, Pekka Jääskeläinen, Johannes IJzerman, Lasse Lehtonen, Timo Viitanen, Markku Makitalo, Jarmo H. Takala. 171-178 [doi]
- Using a genetic algorithm approach to reduce register file pressure during instruction schedulingFlorian Giesemann, Guillermo Payá Vayá, Lukas Gerlach, Holger Blume, Fabian Pflug, Gabriele von Voigt. 179-187 [doi]
- Run-time mapping algorithm for dynamic workloads using process merging transformationsSima Sinaei, Omid Fatemi, Andy D. Pimentel. 188-195 [doi]
- DVFS-enabled power-performance trade-off in MPSoC SW application mappingGereon Onnebrink, Florian Walbroel, Jonathan Klimt, Rainer Leupers, Gerd Ascheid, Luis Gabriel Murillo, Stefan Schürmans, Xiaotao Chen, YwhPyng Harn. 196-202 [doi]
- Energy-efficient scheduling of throughput-constrained streaming applications by periodic mode switchingSobhan Niknam, Todor Stefanov. 203-212 [doi]
- Relaxed subgraph execution model for the throughput evaluation of IBSDF graphsHamza Deroui, Karol Desnos, Jean-François Nezan, Alix Munier Kordon. 213-220 [doi]
- A new state model for DRAMs using Petri NetsMatthias Jung 0001, Kira Kraft, Norbert Wehn. 221-226 [doi]
- Virtual environment for developing real-time image processing for vehicle controlYuranan Kitrungrotsakul, Kiyofumi Tanaka, Masanobu Hashimoto, Shuichi Onishi. 227-232 [doi]
- Supervised testing of concurrent software in embedded systemsJasmin Jahic, Thomas Kuhn, Matthias Jung 0001, Norbert Wehn. 233-238 [doi]
- Task graph mapping and scheduling on heterogeneous architectures under communication constraintsAndreas Emeretlis, T. Tsakoulis, George Theodoridis, Panayiotis Alefragis, Nikos S. Voros. 239-244 [doi]
- Special session on architectures and design tools for secure embedded systemsFrancesco Regazzoni. 245 [doi]
- Location-based leakages: New directions in modeling and exploitingChristos Andrikos, Giorgos Rassias, Liran Lerman, Kostas Papagiannopoulos, Lejla Batina. 246-252 [doi]
- Survey of secure processorsSuman Sau, Jawad Haj-Yahya, Ming Ming Wong, Kwok-Yan Lam, Anupam Chattopadhyay. 253-260 [doi]
- Pipelined FPGA coprocessor for elliptic curve cryptography based on residue number systemPedro Miguens Matutino, Juvenal Araujo, Leonel Sousa, Ricardo Chaves. 261-268 [doi]
- Hiding side-channel leakage through hardware randomization: A comprehensive overviewNele Mentens. 269-272 [doi]
- The design space of the number theoretic transform: A surveyFelipe Valencia, Ayesha Khalid, Elizabeth O'Sullivan, Francesco Regazzoni. 273-277 [doi]
- Hardware accelerators for financial applications in HDL and High Level SynthesisIoannis Stamoulias, Christoforos Kachris, Dimitrios Soudris. 278-285 [doi]
- Thermal characterization of next-generation workloads on heterogeneous MPSoCsArman Iranfar, Federico Terraneo, William Andrew Simon, Leon Dragic, Igor Piljic, Marina Zapater, William Fornaciari, Mario Kovac, David Atienza. 286-291 [doi]
- Access-aware DRAM failure-rate estimation under relaxed refresh operationsKonstantinos Tovletoglou, Dimitrios S. Nikolopoulos, Georgios Karakonstantis. 292-299 [doi]
- A software-defined architecture and prototype for disaggregated memory rack scale systemsDimitris Syrivelis, Andrea Reale, Kostas Katrinis, Ilias Syrigos, Maciej Bielski, Dimitris Theodoropoulos, Dionisios N. Pnevmatikatos, Georgios Zervas. 300-307 [doi]
- The ANTAREX tool flow for monitoring and autotuning energy efficient HPC systemsCristina Silvano, Giovanni Agosta, Jorge G. Barbosa, Andrea Bartolini, Andrea R. Beccari, Luca Benini, João Bispo, João M. P. Cardoso, Carlo Cavazzoni, Stefano Cherubin, Radim Cmar, Davide Gadioli, Candida Manelfi, Jan Martinovic, Ricardo Nobre, Gianluca Palermo, Martin Palkovic, Pedro Pinto, Erven Rohou, Nico Sanna, Katerina Slaninová. 308-316 [doi]