Table of Contents

• Accurate LLVM IR to Binary CFGs Mapping for Simulation of Optimized Embedded SoftwareAlessandro Cornaglia, Alexander Viehl, Oliver Bringmann 0001. 3-15 [doi]
• RVfplib: A Fast and Compact Open-Source Floating-Point Emulation Library for Tiny RISC-V ProcessorsMatteo Perotti, Giuseppe Tagliavini, Stefan Mach, Luca Bertaccini, Luca Benini. 16-32 [doi]
• Exploiting Similarity in Evolutionary Product Design for Improved Design Space ExplorationLuise Müller, Kai Neubauer, Christian Haubelt. 33-49 [doi]
• Automatic Search-Space Compression in System-Level Design Space Exploration Using Deep Generative ModelsValentina Richthammer, Michael Glaß. 50-61 [doi]
• A Case for Partial Co-allocation Constraints in Compressed CachesDaniel Rodrigues Carvalho, André Seznec. 65-77 [doi]
• PoCL-R: A Scalable Low Latency Distributed OpenCL RuntimeJan Solanti, Michal Babej, Julius Ikkala, Vinod Kumar Malamal Vadakital, Pekka Jääskeläinen. 78-94 [doi]
• An Analytical Model for Loop Tiling TransformationVasilios I. Kelefouras, Karim Djemame, Georgios Keramidas, Nikolaos S. Voros. 95-107 [doi]
• Interference-Aware Workload Placement for Improving Latency Distribution of Converged HPC/Big Data Cloud InfrastructuresAchilleas Tzenetopoulos, Dimosthenis Masouros, Sotirios Xydis, Dimitrios Soudris. 108-123 [doi]
• Energy-Efficient and High-Throughput CNN Inference on Embedded CPUs-GPUs MPSoCsErqian Tang, Svetlana Minakova, Todor P. Stefanov. 127-143 [doi]
• Evaluating System Identification Methods for Predicting Thermal Dissipation of Heterogeneous SoCsJoel Öhrling, Sébastien Lafond, Dragos Truscan. 144-160 [doi]
• Embeddings of Task Mappings to Multicore SystemsAndrés Goens, Jerónimo Castrillón. 161-176 [doi]
• RT-LIFE: Portable RISC-V Interface for Real-Time Lightweight Security EnforcementChristoph Spang 0001, Florian Meisel, Andreas Koch 0001. 179-194 [doi]
• Phase-Aware CPU Workload ForecastingErika S. Alcorta, Pranav Rama, Aswin Ramachandran, Andreas Gerstlauer. 195-209 [doi]
• WhiskEras 2.0: Fast and Accurate Whisker Tracking in RodentsPetros Arvanitis, Jan-Harm L. F. Betting, Laurens W. J. Bosman, Zaid Al-Ars, Christos Strydis. 210-225 [doi]
• Strictly Periodic Scheduling of Cyclo-Static Dataflow ModelsSam Nicholas Kouteili, Francesca Spagnuolo, Bruno Bodin. 229-241 [doi]
• Efficient Operator Sharing Modulo Scheduling for Sum-Product Network Inference on FPGAsHanna Kruppe, Lukas Sommer, Lukas Weber, Julian Oppermann, Cristian Axenie, Andreas Koch 0001. 242-258 [doi]
• A Framework for Fixed Priority Periodic Scheduling Synthesis from Synchronous Data-Flow GraphsHai Nam Tran, Alexandre Honorat, Shuvra S. Bhattacharyya, Jean-Pierre Talpin, Thierry Gautier, Loïc Besnard. 259-271 [doi]
• Hard Edges: Hardware-Based Control-Flow Integrity for Embedded DevicesGeorge Christou, Giorgos Vasiliadis, Elias Athanasopoulos, Sotiris Ioannidis. 275-287 [doi]
• ROCKY: Rotation Countermeasure for the Protection of Keys and Other Sensitive DataKonstantina Miteloudi, Lejla Batina, Joan Daemen, Nele Mentens. 288-299 [doi]
• Deep Learning Techniques for Side-Channel Analysis on AES Datasets Collected from Hardware and Software PlatformsTanu Shree Rastogi, Elif Bilge Kavun. 300-316 [doi]
• EDRA: A Hardware-Assisted Decoupled Access/Execute Framework on the Digital Market - Invited PaperDimitris Theodoropoulos, Andreas Brokalakis, Nikolaos Alachiotis, Dionisios N. Pnevmatikatos. 319-330 [doi]
• Modeling the Scalability of the EuroExa Reconfigurable Accelerators - Preliminary Results - Invited PaperPanagiotis Miliadis, Panagiotis Mpakos, Nikela Papadopoulou, Georgios I. Goumas, Dionisios N. Pnevmatikatos. 331-341 [doi]
• The Known Unknowns: Discovering Trade-Offs Between Heterogeneous Code Changes - Invited PaperChristos P. Lamprakos, Charalampos Marantos, Lazaros Papadopoulos, Dimitrios Soudris. 342-353 [doi]
• Towards Efficient HW Acceleration in Edge-Cloud Infrastructures: The SERRANO Approach - Invited PaperAggelos Ferikoglou, Ioannis Oroutzoglou, Argyris Kokkinis, Dimitrios Danopoulos, Dimosthenis Masouros, Efthymios Chondrogiannis, Aitor Fernández Gómez, Aristotelis Kretsis, Panagiotis C. Kokkinos, Emmanouel A. Varvarigos, Kostas Siozios. 354-367 [doi]
• Cross-domain Modelling of Verification and Validation Workflows in the Large Scale European Research Project VALU3S - Invited PaperThomas Bauer, Joseba Andoni Agirre, David Fürcho, Wolfgang Herzner, Bob Hruska, Mustafa Karaca, David Pereira, José Proença, Rupert Schlick, Robert Sicher, Ales Smrcka, Ugur Yayan, Behrooz Sangchoolie. 368-382 [doi]
• Hardware/Software Co-Design of an Automatically Generated Analog NNRoland Müller, Maximilian Oppelt, Bijoy Kundu, Bangalore Ramesh Akshay Agashe, Thomas Thönes, Elmar Herzer, Claudia Schuhmann, Soumitro Chakrabarty, Christian Kroos, Loreto Mateu. 385-400 [doi]
• Mitigating the Effects of RRAM Process Variation on the Accuracy of Artificial Neural NetworksMarkus Fritscher, Johannes Knödtel, Maen Mallah, Stefan Pechmann, Emilio Pérez-Bosch Quesada, Tommaso Rizzi, Christian Wenger, Marc Reichenbach. 401-417 [doi]
• SparseMAX: Accelerating Quantum Neural Networks on GPU Clusters Using Sparse-Matrix KernelsAnand Ravishankar, Santhi Natarajan, A. Bharathi Malakreddy. 418-431 [doi]
• SEC-Learn: Sensor Edge Cloud for Federated Learning - Invited PaperPatrick Aichroth, Christoph Antes, Pierre Gembatzka, Holger Graf, David S. Johnson, Matthias Jung 0001, Thomas Kämpfe, Thomas Kleinberger, Thomas Köllmer, Thomas Kuhn, Christoph Kutter, Jens Krüger 0004, Dominik Marek Loroch, Hanna M. Lukashevich, Nellie Laleni, Lei Zhang, Johannes Leugering, Rodrigo Martín Fernández, Loreto Mateu, Shaown Mojumder, Benjamin Prautsch, Ferdinand Pscheidl, Karsten Roscher, Sören Schneickert, Frank Vanselow, Paul Wallbott, Oliver Walter, Nico Weber. 432-448 [doi]
• (When) Do Multiple Passes Save Energy?Louis Narmour, Tomofumi Yuki, Sanjay V. Rajopadhye. 451-466 [doi]
• Dynamic Network Selection for the Object Detection Task: Why It Matters and What We (Didn't) AchieveEmanuele Vitali, Anton Lokhmotov, Gianluca Palermo. 467-480 [doi]
• Sharing-Aware Data Mapping in Software Transactional MemoryDouglas Pereira Pasqualin, Matthias Diener, André Rauber Du Bois, Maurício Lima Pilla. 481-492 [doi]
• Dead-Ends in FPGAs for Database AccelerationAnna Drewes, Martin Koppehel, Thilo Pionteck. 493-504 [doi]
• The Challenge of Classification Confidence Estimation in Dynamically-Adaptive Neural NetworksFrancesco Dall'Occo, Andrés Bueno-Crespo, José L. Abellán, Davide Bertozzi, Michele Favalli. 505-522 [doi]