Abstract is missing.
- High-Level Synthesis of Digital Circuits from Template Haskell and SDF-APH. H. Folmer, R. De Groote, Marco Jan Gerrit Bekooij. 3-27 [doi]
- Implementing Synthetic Aperture Radar Backprojection in Chisel - A Field ReportNiklas Rother, Christian Fahnemann, Holger Blume. 28-42 [doi]
- EasyHBM: Simple and Fast HBM Access for FPGAs Using High-Level-SynthesisLars Schwenger, Philipp Holzinger, Dietmar Fey, Hector Gerardo Muñoz Hernandez, Marc Reichenbach. 43-57 [doi]
- TREAM: A Tool for Evaluating Error Resilience of Tree-Based Models Using Approximate MemoryMikail Yayla, Zahra Valipour Dehnoo, Mojtaba Masoudinejad, Jian-Jia Chen. 61-73 [doi]
- Split'n'Cover: ISO 26262 Hardware Safety Analysis with SystemCDenis Uecker, Matthias Jung 0001. 74-89 [doi]
- Tagged Geometric History Length Access Interval Prediction for Tightly Coupled Memory SystemsViktor Razilov, Robert Wittig, Emil Matús, Gerhard P. Fettweis. 90-100 [doi]
- NanoController: A Minimal and Flexible Processor Architecture for Ultra-Low-Power Always-On System State ControllersMoritz Weißbrich, Guillermo Payá Vayá. 103-119 [doi]
- ControlPULP: A RISC-V Power Controller for HPC Processors with Parallel Control-Law Computation AccelerationAlessandro Ottaviano, Robert Balas, Giovanni Bambini, Corrado Bonfanti, Simone Benatti, Davide Rossi, Luca Benini, Andrea Bartolini. 120-135 [doi]
- CASA: An Approach for Exposing and Documenting Concurrency-Related Software PropertiesJasmin Jahic, Volkan Doganci, Hubert Gehring. 139-154 [doi]
- High-Level Simulation of Embedded Software Vulnerabilities to EM Side-Channel AttacksAditya Thimmaiah, Vishnuvardhan V. Iyer, Andreas Gerstlauer, Michael Orshansky. 155-170 [doi]
- A Design Space Exploration Methodology for Enabling Tensor Train Decomposition in Edge DevicesMilad Kokhazadeh, Georgios Keramidas, Vasilios I. Kelefouras, Iakovos Stamoulis. 173-186 [doi]
- Study of DNN-Based Ragweed Detection from DronesMartin Lechner, Lukas Steindl, Axel Jantsch. 187-199 [doi]
- PULP-TrainLib: Enabling On-Device Training for RISC-V Multi-core MCUs Through Performance-Driven AutotuningDavide Nadalini, Manuele Rusci, Giuseppe Tagliavini, Leonardo Ravaglia, Luca Benini, Francesco Conti 0001. 200-216 [doi]
- The Impact of Dynamic Storage Allocation on CPython Execution Time, Memory Footprint and Energy Consumption: An Empirical StudyChristos P. Lamprakos, Lazaros Papadopoulos, Francky Catthoor, Dimitrios Soudris. 219-234 [doi]
- Application Runtime Estimation for AURIX Embedded MCU Using Deep LearningFlorian Fricke, Stefan Scharoba, Sebastian Rachuj, Andreas Konopik, Florian Kluge, Georg Hofstetter, Marc Reichenbach. 235-249 [doi]
- A Hybrid Performance Prediction Approach for Fully-Connected Artificial Neural Networks on Multi-core PlatformsQuentin Dariol, Sebastien Le Nours, Sébastien Pillement, Ralf Stemmer, Domenik Helms, Kim Grüttner. 250-263 [doi]
- A Smart HW-Accelerator for Non-uniform Linear Interpolation of ML-Activation FunctionsSebastian Siegfried Prebeck, Wafic Lawand, Mounika Vaddeboina, Wolfgang Ecker. 267-282 [doi]
- Hardware-Aware Evolutionary Filter PruningChristian Heidorn, Nicolai Meyerhöfer, Christian Schinabeck, Frank Hannig, Jürgen Teich. 283-299 [doi]
- Obfuscating the Hierarchy of a Digital IPGiorgi Basiashvili, Zail Ul Abideen, Samuel Pagliarini. 303-314 [doi]
- On the Effectiveness of True Random Number Generators Implemented on FPGAsDavide Galli, Andrea Galimberti, William Fornaciari, Davide Zoni. 315-326 [doi]
- SIDAM: A Design Space Exploration Framework for Multi-sensor Embedded Systems Powered by Energy HarvestingPierre-Louis Sixdenier, Stefan Wildermann, Daniel Ziegler, Jürgen Teich. 329-345 [doi]
- A Data-Driven Approach to Lightweight DVFS-Aware Counter-Based Power Modeling for Heterogeneous PlatformsSergio Mazzola, Thomas Benz, Björn Forsberg, Luca Benini. 346-361 [doi]
- A Critical Assessment of DRAM-PIM Architectures - Trends, Challenges and SolutionsChirag Sudarshan, Mohammad Hassani Sadi, Lukas Steiner, Christian Weis, Norbert Wehn. 362-379 [doi]
- SafeDX: Standalone Modules Providing Diverse Redundancy for Safety-Critical ApplicationsRamon Canal, Francisco Bas, Sergi Alcaide, Guillem Cabo, Pedro Benedicte, Francisco Fuentes, Feng Chang, Ilham Lasfar, Jaume Abella 0001. 383-393 [doi]
- HW/SW Acceleration of Multiple Workloads Within the SERRANO's Computing Continuum - Invited PaperArgyris Kokkinis, Aggelos Ferikoglou, Ioannis Oroutzoglou, Dimitrios Danopoulos, Dimosthenis Masouros, Kostas Siozios. 394-405 [doi]
- LSTM Acceleration with FPGA and GPU Devices for Edge Computing Applications in B5G MECDimitrios Danopoulos, Ioannis Stamoulias, George Lentaris, Dimosthenis Masouros, Ioannis Kanaropoulos, Andreas Kosmas Kakolyris, Dimitrios Soudris. 406-419 [doi]
- The TEXTAROSSA Approach to Thermal Control of Future HPC SystemsWilliam Fornaciari, Federico Terraneo, Giovanni Agosta, Giuseppe Zummo, Luca Saraceno, Giorgia Lancione, Daniele Gregori, Massimo Celino. 420-433 [doi]