Abstract is missing.
- ParTriCluster: A Scalable Parallel Algorithm for Gene Expression AnalysisRenata Braga Araújo, Guilherme Henrique Trielli Ferreira, Gustavo Henrique Orair, Wagner Meira Jr., Renato Ferreira, Dorgival Olavo Guedes Neto. 3-10 [doi]
- Towards Production Code Effective Portability among Vector Machines and Microprocessor-Based ArchitecturesAlvaro Luiz Fazenda, Eduardo Hidenori Enari, Luiz Flavio Rodrigues, Jairo Panetta. 11-20 [doi]
- Data Segmentation Management Infrastructure in a Database GridReinaldo Lourenso, Sergio Takeo Kofuji. 21-27 [doi]
- Detecting Malicious Manipulation in Grid EnvironmentsFelipe Martins, Márcio Maia, Rossana M. de Castro Andrade, Aldri L. dos Santos, José Neuman de Souza. 28-35 [doi]
- Policy-based Resource Allocation in Hierarchical Virtual Organizations for Global GridsKyong Hoon Kim, Rajkumar Buyya. 36-46 [doi]
- A Speculative Trace Reuse Architecture with Reduced Hardware RequirementsMaurício L. Pilla, Bruce R. Childers, Amarildo T. da Costa, Felipe M. G. França, Philippe Olivier Alexandre Navaux. 47-54 [doi]
- Controlling the Power and Area of Neural Branch Predictors for Practical Implementation in High-Performance ProcessorsDaniel A. Jiménez, Gabriel H. Loh. 55-62 [doi]
- The mDTSVLIW: a Multi-Threaded Trace-based VLIW ArchitecturePeter Rounce, Alberto Ferreira de Souza. 63-72 [doi]
- GerpavGrid: using the Grid to maintain the city road systemCésar A. F. De Rose, Tiago C. Ferreto, Marcelo B. de Farias, Vladimir G. Dias, Walfredo Cirne, Milena P. M. Oliveira, Katia B. Saikoski, Maria Luiza Danieleski. 73-80 [doi]
- A Run-time System for Efficient Execution of Scientific Workflows on Distributed EnvironmentsGeorge Teodoro, Tulio Tavares, Renato Ferreira, Tahsin M. Kurç, Wagner Meira Jr., Dorgival Olavo Guedes Neto, Tony Pan, Joel H. Saltz. 81-90 [doi]
- Dual-Thread Speculation: Two Threads in the Machine are Worth Eight in the BushFredrik Warg, Per Stenström. 91-98 [doi]
- Characterizing the Performance of Data Management Systems on Hyper-Threaded ArchitecturesWessam Hassanein, Moustafa A. Hammad, Layali K. Rashid. 99-106 [doi]
- Ultra-Fast CPU Performance Prediction: Extending the Monte Carlo ApproachRam Srinivasan, Jeanine Cook, Olaf M. Lubeck. 107-116 [doi]
- Scalable Value-Cache Based Compression Schemes for MultiprocessorsMartin Thuresson, Per Stenström. 117-124 [doi]
- Tuning Mechanism for Two-Level Cache Hierarchy Intended for Instruction Caches and Low Energy ConsumptionAbel Guilhermino S. Filho, Pablo Viana, Edna Barros, Manoel Eusebio de Lima. 125-132 [doi]
- Applying the zeros switch-off technique to reduce static energy in data cachesRafael Ubal, Julio Sahuquillo, Salvador Petit, Pedro López. 133-140 [doi]
- 32-core CMP with multi-sliced L2: 2 and 4 cores sharing a L2 sliceMario Donato Marino. 141-150 [doi]
- Combining Source Routing and Dynamic Fault ToleranceFrank Olaf Sem-Jacobsen, Olav Lysne, Tor Skeie. 151-158 [doi]
- Runtime System Support for Running Applications with Dynamic and Asynchronous Task Parallelism in Software DSM SystemsRafael Mendes, Lauro Whately, Maria Clicia Stelling de Castro, Cristiana Bentes, Claudio Luis de Amorim. 159-166 [doi]
- Scalable Parallel Implementation of Bayesian Network to Junction Tree Conversion for Exact InferenceVasanth Krishna Namasivayam, Animesh Pathak, Viktor K. Prasanna. 167-176 [doi]
- Reconfigurable System with Virtuoso Real-Time Kernel and TEV EnvironmentM. C. Andrade, Célio Estevan Morón, José Hiroki Saito. 177-184 [doi]
- Virtual-Machine-based Intrusion Detection on File-aware Block Level StorageYouhui Zhang, Yu Gu, Hongyi Wang, Dongsheng Wang. 185-192 [doi]