Abstract is missing.
- Accurate and Low-Overhead Dynamic Detection and Prediction of Program Phases Using Branch SignaturesBalaji Vijayn, Dmitry V. Ponomarev. 3-10 [doi]
- Aggressive Scheduling and Speculation in Multithreaded Architectures: Is it Worth its Salt?Jason Loew, Dmitry Ponomarev. 11-18 [doi]
- An Optimization Mechanism Intended for Two-Level Cache Hierarchy to Improve Energy and Performance Using the NSGAII AlgorithmAbel G. Silva-Filho, Carmelo J. A. Bastos Filho, Davi M. A. Falcão, Filipe R. Cordeiro, Rodrigo M. C. S. Castro. 19-26 [doi]
- On Simulated Annealing for the Scheduling of Parallel ApplicationsRodrigo Fernandes de Mello, Luciano José Senger. 29-36 [doi]
- Controlling Processes Reassignment in BSP ApplicationsRodrigo Da Rosa Righi, Laércio Lima Pilla, Alexandre Carissimi, Philippe Olivier Alexandre Navaux. 37-44 [doi]
- A High Performance Massively Parallel Approach for Real Time Deformable Body Physics SimulationThiago S. M. C. de Farias, Mozart W. S. Almeida, João Marcelo X. N. Teixeira, Veronica Teichrieb, Judith Kelner. 45-52 [doi]
- A Methodology for Developing High Fidelity Communication Models for Large-Scale Applications Targeted on Multicore SystemsCharles W. Lively, Valerie E. Taylor, Sadaf R. Alam, Jeffrey S. Vetter. 55-62 [doi]
- Selection of the Register File Size and the Resource Allocation Policy on SMT ProcessorsJesús Alastruey, Teresa Monreal, Francisco J. Cazorla, VÃctor Viñals, Mateo Valero. 63-70 [doi]
- ORBIT: Effective Issue Queue Soft-Error Vulnerability Mitigation on Simultaneous Multithreaded Architectures Using Operand Readiness-Based Instruction DispatchXin Fu, Tao Li, José A. B. Fortes. 71-78 [doi]
- Processing Neocognitron of Face Recognition on High Performance Environment Based on GPU with CUDA ArchitectureGustavo Poli, José Hiroki Saito, João F. Mari, Marcelo R. Zorzan. 81-88 [doi]
- Parallel Verified Linear System Solver for Uncertain Input DataMariana Luderitz Kolberg, Márcio Dorn, Luiz Gustavo Fernandes, Gerd Bohlender. 89-96 [doi]
- Applying Virtualization and System Management in a Cluster to Implement an Automated Emulation Testbed for Grid ApplicationsRodrigo N. Calheiros, Mauro Storch, Everton Alexandre, César A. F. De Rose, Marcus Breda. 97-104 [doi]
- Hiding Communication Delays in Clustered MicroarchitecturesRobert J. LaDuca, Joseph J. Sharkey, Dmitry V. Ponomarev. 107-114 [doi]
- Software Synthesis for Hard Real-Time Embedded Systems with Energy ConstraintsEduardo Tavares, Bruno Silva, Paulo Romero Martins Maciel, Pedro Dallegrave. 115-122 [doi]
- A Segmented Bloom Filter Algorithm for Efficient PredictorsMauricio Breternitz Jr., Gabriel H. Loh, Bryan Black, Jeff Rupley, Peter G. Sassone, Wesley Attrot, Youfeng Wu. 123-130 [doi]
- Measuring Operating System Overhead on CMT ProcessorsPetar Radojkovic, Vladimir Cakarevic, Javier Verdú, Alejandro Pajuelo, Roberto Gioiosa, Francisco J. Cazorla, Mario Nemirovsky, Mateo Valero. 133-140 [doi]
- Aspect-Based Patterns for Grid ProgrammingLuis Daniel Benavides Navarro, Rémi Douence, Fabien Hermenier, Jean-Marc Menaud, Mario Südholt. 141-148 [doi]
- A Reconfigurable Run-Time System for Filter-Stream ApplicationsDaniel Fireman, George Teodoro, André Cardoso, Renato Ferreira. 149-156 [doi]
- Using Analytical Models to Efficiently Explore Hardware Transactional Memory and Multi-Core Co-DesignJames Poe, Chang-Burm Cho, Tao Li. 159-166 [doi]
- Performance Sensitivity of NUCA Caches to On-Chip Network ParametersAlessandro Bardine, Manuel Comparetti, Pierfrancesco Foglia, Giacomo Gabrielli, Cosimo Antonio Prete. 167-174 [doi]
- A Software Transactional Memory System for an Asymmetric Processor ArchitectureFelipe Goldstein, Alexandro Baldassin, Paulo Centoducatte, Rodolfo Azevedo, Leonardo A. G. Garcia. 175-182 [doi]
- Transactional WaveCache: Towards Speculative and Out-of-Order DataFlow Execution of Memory OperationsLeandro A. J. Marzulo, Felipe Maia Galvão França, VÃtor Santos Costa. 183-190 [doi]