Table of Contents

• Return-to-one protocol for reducing static power in C-elements of QDI circuits employing m-of-n codesMatheus T. Moreira, Ricardo A. Guazzelli, Ney Laert Vilar Calazans. 1-6 [doi]
• NSP kernel finder - A methodology to find and to build non-series-parallel transistor arrangementsVinicius Neves Possani, Felipe S. Marques, Leomar S. da Rosa Jr., Vinicius Callegaro, André Inácio Reis, Renato P. Ribas. 1-6 [doi]
• Communication software synthesis from UML-ESL modelsThiago Cardoso, Edna Barros, Bruno Prado, Andre Aziz. 1-6 [doi]
• Hardware and software co-design for the AAC audio decoderRenato Coral Sampaio, Pedro de Azevedo Berger, Ricardo Pezzuol Jacobi. 1-6 [doi]
• A low complexity lossless data compressor IP-core for satellite imagesYuri Gonzaga Goncalves da Costa, José Antônio Gomes de Lima, Guilherme Navarro. 1-6 [doi]
• Topological impact on latency and throughput: 2D versus 3D NoC comparisonYan Ghidini, Thais Webber, Edson I. Moreno, Ivan Quadros, Rubem Dutra Ribeiro Fagundes, César A. M. Marcon. 1-6 [doi]
• Current-mode analog integrated circuit for focal-plane image compressionFernanda D. V. R. Oliveira, Hugo de Lemos Haas, José Gabriel Rodríguez Carneiro Gomes, Antonio Petraglia. 1-6 [doi]
• Yield optimization for low power current controlled current conveyorZia Abbas, Marat Yakupov, Mauro Olivieri, Andreas Ripp, Gunter Strube. 1-6 [doi]
• A 50MHz-lGHz wideband low noise amplifier in 130nm CMOS technologyHenrique Luiz Andrade Pimentel, Sergio Bampi. 1-6 [doi]
• A temperature compensated CMOS relaxation oscillator for low power applicationsJefferson B. D. Soldera, Michael Todd Berens, Alfredo Olmos. 1-4 [doi]
• A formally verified deadlock-free routing function in a fault-tolerant NoC architectureAbdulaziz Alhussien, Nader Bagherzadeh, Freek Verbeek, Bernard van Gastel, Julien Schmaltz. 1-6 [doi]
• Top-down design for Low power Multi-bit Sigma-Delta ModulatorHeiner Alarcon Cubas, Joao Navarro Soares Jr.. 1-6 [doi]
• A very low power area efficient CMOS only bandgap referenceEdgar Mauricio Camacho-Galeano, Alfredo Olmos, Andre Vilas Boas. 1-6 [doi]
• Power consumption reduction in MPSoCs through DFSThiago R. da Rosa, Vivian Larrea, Ney Calazans, Fernando Gehm Moraes. 1-6 [doi]
• High throughput hardware design for the Adaptive Loop Filter of the emerging HEVC video codingFabiane Rediess, Luciano Volcan Agostini, Cassio Cristani, Pargles Dall'Oglio, Marcelo Schiavon Porto. 1-5 [doi]
• Kernel analysis for architecture design trade off in convolution-based image filteringJones Yudi Mori, Carlos H. Llanos, Pedro A. Berger. 1-6 [doi]
• A PLL for clock generation with automatic frequency control under TID effectsRicardo Vanni Dallasen, Gilson Inacio Wirth, Thiago Hanna Both. 1-5 [doi]
• Differential mixer with NMOS/PMOS stack at switching stageEverson Martins, Matheus A. Alejandro, Thais V. Fogaca. 1-3 [doi]
• Partitioning-based wirelength estimation technique for Y-routingTuhina Samanta, Hafizur Rahaman, Parthasarathi Dasgupta. 1-6 [doi]
• A pragma based approach for mapping MATLAB applications on a coarse grained reconfigurable architectureOmer Malik, Ahmed Hemani. 1-6 [doi]
• FPGA-based digital direct-conversion transceiver for Nuclear Magnetic Resonance SystemsCecil Accetti R. de A. Melo, Ricardo E. de Souza. 1-5 [doi]
• FPGA design methodology for DSP industrial applications - A case study of a three-phase positive-sequence detectorPaulo Sérgio B. do Nascimento, Francisco A. S. Neves, Helder E. P. de Souza, Marco A. O. Domingues. 1-6 [doi]
• Heterogeneous system-level modeling for small and medium enterprisesSeyed Hosein Attarzadeh Niaki, Gilmar S. Beserra, Nikolaj Andersen, Mathias Verdon, Ingo Sander. 1-6 [doi]
• Memory and communication driven spatio-temporal scheduling on MPSoCsZubair Wadood Bhatti, Narasinga Rao Miniskar, Davy Preuveneers, Roel Wuyts, Yolande Berbers, Francky Catthoor. 1-6 [doi]
• DPA insensitive voltage regulator for contact smart cardsHugo Daniel Hernández, Jonathan Scott, Wilhelmus A. M. Van Noije. 1-4 [doi]
• Extended use of pseudo-flash reset technique for an active pixel with logarithmic compressed responseCarlos A. de Moraes Cruz, Israel L. Marinho, Davies W. de Lima Monteiro. 1-6 [doi]
• FPGA design for real time flaw detection on edges using the LEDges techniqueYgo N. Batista, Cristiano C. de Araujo, Abel G. Silva-Filho. 1-6 [doi]
• Hybrid-on-chip communication architecture for dynamic MP-SoC protectionJohanna Sepúlveda, Guy Gogniat, Ricardo Pires, Wang Jiang Chau, Marius Strum. 1-6 [doi]
• Design-oriented delay model for CMOS inverterFelipe S. Marranghello, André Inácio Reis, Renato P. Ribas. 1-6 [doi]
• Application-Specific Network-on-Chip synthesis with topology-aware floorplanningBo Huang, Song Chen, Wei Zhong, Takeshi Yoshimura. 1-6 [doi]
• A 65nm CMOS 60 GHz class F-E power amplifier for WPAN applicationsSophie Drean, Nathalie Deltimple, Eric Kerherve, Baudouin Martineau, Didier Belot. 1-4 [doi]
• Robust modular Bulk Built-in Current Sensors for detection of transient faultsFrank Sill Torres, Rodrigo Possamai Bastos. 1-6 [doi]
• On-chip 4to20mA reconfigurable current loop transmitter for smart sensor applicationsJefferson Daniel de Barros Soldera, Julio Cesar Saldana, Cesar Giacomini Penteado, Hugo Daniel Hernández, Raul Acosta Hernandez, Fernando Chavez Porras, Marcos A. Valerio, Angelica dos Anjos, Paulo H. Trevisan. 1-6 [doi]
• Multi-bit flip-flop usage impact on physical synthesisCristiano Santos, Ricardo Reis, Guilherme Godoi, Marcos Barros, Fabio Duarte. 1-6 [doi]
• Hardware pipelining of runtime-detected loopsJoão Bispo, João M. P. Cardoso, José Monteiro. 1-6 [doi]