Table of Contents

• Message from conference general chairNorbert Schuhmann. 4-5 [doi]
• Message from program chairsKaijian Shi, Nagi Naganathan. 6 [doi]
• Keynote speaker: "The roadway to innovation"Ronald M. Martino. 29 [doi]
• Plenary speaker: "The pig in the poke? - Strategies to avoid unpleasant surprises with IP on your SoC"Carsten Elgert. 30 [doi]
• Plenary speaker: "Visions of future SoC design: Why heterogeneous architectures and power matter"Volker Politz. 31 [doi]
• Design of 2×VDD logic gates with only 1×VDD devices in nanoscale CMOS technologyPo-Yen Chiu, Ming-Dou Ker. 33-36 [doi]
• An optimal design of a fault tolerant reversible multiplierLafifa Jamal, Md. Mushfiqur Rahman, Hafiz Md. Hasan Babu. 37-42 [doi]
• Layout regularity metric as a fast indicator of high variability circuitsEsraa Swillam, Kareem Madkour, Mohab Anis. 43-48 [doi]
• Architecture and circuit design of parallel processing elements for de novo sequence assemblyYu-Long Huang, Chun-Shen Liu, Yu-Cheng Li, Yi-Chang Lu. 50-54 [doi]
• UWB receiver for breast cancer detection: Comparison between two different approachesXiaolu Guo, Mario R. Casu, Mariagrazia Graziano, Maurizio Zamboni. 55-60 [doi]
• A new data acquisition design for breast cancer detection systemDung Nguyen, Kui Ren, Janet Roveda. 61-66 [doi]
• A 72dBO 11.43mA novel CMOS regulated cascode TIA for 3.125Gb/s optical communicationsYoung-Ho Kim, Sang-Soo Lee. 68-72 [doi]
• PKF: A communication cost reduction schema based on Kalman filter and data prediction for Wireless Sensor NetworksYanqiu Huang, Wanli Yu, Alberto García Ortiz. 73-78 [doi]
• A 6Gb/s 40dB burst-mode digitally adaptive equalizer with reference-calibrated overshoot controlSheng-Kai You, Po-Hsuan Chang, Chia-Ming Tsai. 79-82 [doi]
• Adaptive driver with automatic sense and calibration in CMOS 40LPSushrant Monga. 83-86 [doi]
• Sub-10 µW CMOS wake-up receiver IP for green SoC designsHeinrich Milosiu, Frank Oehler. 88-91 [doi]
• A dual-edged triggered explicit-pulsed level converting flip-flop with a wide operation rangeMei-Wei Chen, Ming-Hung Chang, Pei-Chen Wu, Yi-Ping Kuo, Chun-Lin Yang, Yuan-Hua Chu, Wei Hwang. 92-97 [doi]
• An efficient approach for designing a reversible fault tolerant n-bit carry look-ahead adderHafiz Md. Hasan Babu, Lafifa Jamal, Nazir Saleheen. 98-103 [doi]
• Method for resolving simultaneous same-row access in Dual-Port 8T SRAM with asynchronous dual-clock operationNan-Chun Lien, Ching-Te Chuang, Wen-Rong Wu. 105-109 [doi]
• A 40nm 1.0Mb 6T pipeline SRAM with digital-based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS tracking and Adaptive Voltage Detector for boosting controlWei-Nan Liao, Nan-Chun Lien, Chi-Shin Chang, Li-Wei Chu, Hao-I Yang, Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang, Ming-Hsien Tu, Huan-Shun Huang, Jian-Hao Wang, Paul-Sen Kan, Yong-Jyun Hu. 110-115 [doi]
• A BCH decoding architecture with mixed parallelization degrees for flash controller applicationsJens Spinner, Jürgen Freudenberger, Christoph Baumhof, Axel Mehnert, Richard Willems. 116-121 [doi]
• Development of advanced diagnostic functions in very high volume automotive sensor applicationsMartin Krey, Daniel Sabotta, Fabian Zahn, Karl-Ragmar Riemschneider, Rasmus Rettig. 123-128 [doi]
• Light field data processor design for depth estimation using confidence-assisted disparitiesShih-Chieh Fan Chiang, Po-Hsiang Hsu, Yi-Chang Lu. 129-133 [doi]
• Analysis and implementation of Discrete Wavelet Transform for compressing four-dimensional light field dataChun-Liang Kuo, Yang-Yao Lin, Yi-Chang Lu. 134-138 [doi]
• Banquet speaker: "The MP3 story and more: Perceptual audio coding from its beginnings to the present"Jürgen Herre. 139 [doi]
• Tutorial: Methodology for designing reliable clock networksTaewhan Kim. 141 [doi]
• Tutorial: The uncertain end to siliconAndrew Marshall, Karan Bhatia. 143 [doi]
• Plenary speaker: "Processor-to-memory interface design methodologies for energy and performance efficiencies"Bill Huffman. 145 [doi]
• Multiple terminal reduction methodGoro Suzuki. 147-152 [doi]
• High-level TSV resource sharing and optimization for TSV based 3D IC designsByungHyun Lee, Taewhan Kim. 153-158 [doi]
• Latency-optimization synthesis with module selection for digital microfluidic biochipsChia-Hung Liu, Kuang-Cheng Liu, Juinn-Dar Huang. 159-164 [doi]
• Advanced clock schemes with dead time techniques for high voltage charge pumpsLufei Shen, Klaus Hofmann. 166-171 [doi]
• ViLoCoN - An ultra-lightweight lossless VLSI video codecShani Rehana, Or Turgeman, Ran Manevich, Avinoam Kolodny. 172-177 [doi]
• Power aware transformation of bandlimited signalsPrakash Krishnamoorthy, Ramesh C. Tekumalla. 178-183 [doi]
• Treat thy secondary (ALMOST) like thy primary- A fair arbiter in master-slave configurationBallori Banerjee, Jim Vomero. 184-190 [doi]
• A wide range programmable duty cycle correctorAshok Jaiswal, Yuan Fang, Kashif Nawaz, Klaus Hofmann. 192-196 [doi]
• Morpack Cube: A portable 3D heterogeneous system integration platformChun-Chieh Chiu, Chih-Hsing Lin, Chih-Chyau Yang, Yi-Jun Liu, Ssu-Ying Chen, Jin-Ju Chue, Chih-Ting Kuo, Gang-Neng Sung, Chun-Pin Lin, Chien-Ming Wu, Chun-Ming Huang. 197-202 [doi]
• Real-time efficient FPGA implementation of aes algorithmMazen El Maraghy, Salma Hesham, Mohamed A. Abd El ghany. 203-208 [doi]
• Novel time-multiplexing bidirectional on-chip networkChun-Jen Wei, Yi-Yao Weng, Wen-Chung Tsai, Sao-Jie Chen, Yu Hen Hu. 210-215 [doi]
• Coding algorithms for network on a chipAyman A. Salem, Mohamed A. Abd El ghany, Klaus Hofmann. 216-221 [doi]
• High-performance adaption of ARM processors into Network-on-Chip architecturesTung Nguyen, Duy-Hieu Bui, Hai-Phong Phan, Trong-Trinh Dang, Xuan-Tu Tran. 222-227 [doi]
• Plenary speaker: "Power-centric timing optimization for low power CPU hardening"Jonathan Young. 229 [doi]
• Effective signal region based analog mixed signal design considering variations and applicationsJanet Roveda, Dung Nguyen, Linda Powers, Kui Ren, Jerrie Fairbanks. 233-238 [doi]
• DLL-based programmable clock multiplier using differential toggle-pulsed latchChorng-Sii Hwang, Ting-Li Chu, Po-Hsun Chen. 239-243 [doi]
• Design-for-testability automation of mixed-signal integrated circuitsSergey G. Mosin. 244-249 [doi]
• Scalable system map library for address map and data integrity verificationPrashanth Srinivasa. 250-255 [doi]
• A novel approach to design a reversible shifter circuit using DNATanvir Ahmed, Ankur Sarker, Mohd. Istiaq Sharif, S. M. Mahbubur Rashid, Md. Atiqur Rahman, Hafiz Md. Hasan Babu. 256-261 [doi]
• Sealed mask ROM wafer with 5 mm magnetic resonant coupling for long-term digital data preservationHiroyuki Ochi, Toshihiko Ota, Ataru Yamaoka, Hiromasa Watanabe, Yohei Kondo, Nobuyuki Tokuda, Hiroyuki Taguchi, Taketoshi Matsumoto, Tomoki Akai, Hikaru Kobayashi, Shigeki Imai. 262-266 [doi]
• Implementation and performance analysis of variable latency addersAli Sayyed, Luciano Lavagno, Shah Khalid, Najeeb Ur Rahman. 267-272 [doi]
• Quotient prediction for low power divisionPrakash Krishnamoorthy, Ramesh C. Tekumalla. 273-277 [doi]
• Sleep transistor design in 28nm CMOS technologyKaijian Shi. 278-283 [doi]
• SOSoC, a Linux framework for System Optimization using System on ChipOlivier Nasrallah, Wolfram Luithardt, Daniel Rossier, Alberto Dassatti, Jerome Stadelmann, Xavier Blanc, Nuria Pazos, Florian Sauser, Serge Monnerat. 284-289 [doi]
• An analytical, dynamic, power-performance router model for run-time NoC optimizationsDavide Zoni, Federico Terraneo, William Fornaciari. 290-295 [doi]
• Rapid prototyping of a portable HW/SW co-design on the virtual zynq platform using SystemCPhilipp Wehner, Max Ferger, Diana Göhringer, Michael Hübner. 296-300 [doi]
• A generic, scalable reconfiguration infrastructure for sensor networks functionality adaptionAlexander Biedermann, Boris Dreyer, Sorin A. Huss. 301-306 [doi]
• A formalism of the specifications for library developmentJung Kyu Chae, Paul Mougeat, Jean-Arnaud Francois, Roselyne Chotin-Avot, Habib Mehrez. 307-312 [doi]
• Tutorial: Macro-modeling for solving SOC physical design automation problemsRoman Bazylevych, Lubov Bazylevych. 314 [doi]
• Tutorial: Digital microfluidic biochips: Towards hardware/software co-design and cyber-physical system integrationTsung-Yi Ho, Juinn-Dar Huang, Paul Pop. 316-317 [doi]
• Low-power signal integrity trainings for multi-clock source-synchronous memory systemsYuan Fang, Ashok Jaiswal, Klaus Hofmann. 319-324 [doi]
• A disturb-free subthreshold 9T SRAM cell with improved performance and variation toleranceChien-Yu Lu, Ching-Te Chuang. 325-329 [doi]
• Equal length routingGerard M. Blair. 331-335 [doi]
• Finding ground traces using the laplacian of the meshes of the associated graphCristian E. Onete, Maria Cristina C. Onete. 336-341 [doi]
• Noise immunity improvement in the RESET signal of DDR3 SDRAM memory moduleSeung Mo Jung, Jong Hyun Seok, Ho Jin Yoo, Do-Hyung Kim, You Keun Han, Woo-Seop Kim, Joo-Sun Choi, Jun Dong Cho. 343-348 [doi]
• A comprehensive operand-aware dynamic clock gating scheme for low-power Domino LogicSalim Farah, Magdy Bayoumi. 349-354 [doi]
• Design automation flow for voltage adaptive optimum granularity LITHE for sequential circuitsVenkat Krishnan Balasubramanian, Hao Xu, Ranga Vemuri. 355-360 [doi]
• A robust medium access mechanism for millimeter-wave Wireless Network-on-Chip architectureNaseef Mansoor, Manoj Prashanth Yuvaraj, Amlan Ganguly. 362-367 [doi]
• Integrated routing and channel arbitration in overlaid mesh WiNoCRuizhe Wu, Dan Zhao. 368-373 [doi]
• A low cost method to tolerate soft errors in the NoC router control planeChanglin Chen, Sorin Dan Cotofana. 374-379 [doi]