Automatic Random Logic Layout Synthesis - a Module Generator Approach (VlSI, Silicon Compilation, Design Automation, Cell Synthesis, Grid)

Meng-Lin Yu. Automatic Random Logic Layout Synthesis - a Module Generator Approach (VlSI, Silicon Compilation, Design Automation, Cell Synthesis, Grid). PhD thesis, University of Illinois Urbana-Champaign, USA, 1986. [doi]

Abstract

Abstract is missing.