VLSI-SoC: Design Trends - 28th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2020, Salt Lake City, UT, USA, October 6-9, 2020, Revised and Extended Selected Papers - researchr publication

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Andrea Calimera, Pierre-Emmanuel Gaillardon, Kunal Korgaonkar, Shahar Kvatinsky, Ricardo Reis 0001, editors, VLSI-SoC: Design Trends - 28th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2020, Salt Lake City, UT, USA, October 6-9, 2020, Revised and Extended Selected Papers. Volume 621 of IFIP Advances in Information and Communication Technology, Springer, 2021. [doi]

Conference: vlsi2021

Abstract is missing.

Low-Power High-Speed ADCs for ADC-Based Wireline Receivers in 22 nm FDSOIDavid Cordova, Wim Cops, Yann Deval, François Rivet, Hervé Lapuyade, Nicolas Nodenot, Yohan Piccin. 1-19 [doi]

Mixed-Mode Signal Processing for Implementing MCMC MIMO DetectorAmin Aghighi, Behrouz Farhang-Boroujeny, Armin Tajalli. 21-37 [doi]

Low Power Current-Mode Relaxation Oscillators for Temperature and Supply Voltage MonitoringShanshan Dai, Caleb R. Tulloss, Xiaoyu Lian, Kangping Hu, Sherief Reda, Jacob K. Rosenstein. 39-63 [doi]

Fully-Autonomous SoC Synthesis Using Customizable Cell-Based Analog and Mixed-Signal Circuits GenerationTutu Ajayi, Sumanth Kamineni, Morteza Fayazi, Yaswanth K. Cherivirala, Kyumin Kwon, Shourya Gupta, Wenbo Duan, Jeongsup Lee, Chien-Hen Chen, Mehdi Saligane, Dennis Sylvester, David T. Blaauw, Ronald Dreslinski Jr., Benton H. Calhoun, David D. Wentzloff. 65-85 [doi]

Assessing the Configuration Space of the Open Source NVDLA Deep Learning Accelerator on a Mainstream MPSoC PlatformAlessandro Veronesi, Davide Bertozzi, Milos Krstic. 87-112 [doi]

SAT-Based Mapping of Data-Flow Graphs onto Coarse-Grained Reconfigurable ArraysYukio Miyasaka, Masahiro Fujita, Alan Mishchenko, John Wawrzynek. 113-131 [doi]

Learning Based Timing Closure on Relative Timed DesignTannu Sharma, Sumanth Kolluru, Kenneth S. Stevens. 133-148 [doi]

Multilevel Signaling for High-Speed Chiplet-to-Chiplet CommunicationRakshith Saligram, Ankit Kaul, Muhannad S. Bakir, Arijit Raychowdhury. 149-178 [doi]

From Informal Specifications to an ABV Framework for Industrial Firmware VerificationSamuele Germiniani, Moreno Bragaglio, Graziano Pravadelli. 179-204 [doi]

Modular Functional Testing: Targeting the Small Embedded Memories in GPUsJosie Esteban Rodriguez Condia, Matteo Sonza Reorda. 205-233 [doi]

RAT: A Lightweight Architecture Independent System-Level Soft Error Mitigation TechniqueJonas Gava, Ricardo Reis 0001, Luciano Ost. 235-253 [doi]

SANSCrypt: Sporadic-Authentication-Based Sequential Logic EncryptionYinghua Hu, Kaixin Yang, Shahin Nazarian, Pierluigi Nuzzo. 255-278 [doi]

3D Nanofabric: Layout Challenges and Solutions for Ultra-scaled Logic DesignsEdouard Giacomin, Jürgen Bömmels, Julien Ryckaert, Francky Catthoor, Pierre-Emmanuel Gaillardon. 279-300 [doi]

3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact ModelArnaud Poittevin, Chhandak Mukherjee, Ian O'Connor, Cristell Maneux, Guilhem Larrieu, Marina Deng, Sébastien Le Beux, François Marc, Aurélie Lecestre, Cédric Marchand 0002, Abhishek Kumar. 301-321 [doi]

Statistical Array Allocation and Partitioning for Compute In-Memory FabricsBrian Crafton, Samuel Spetalnick, Gauthaman Murali, Tushar Krishna, Sung Kyu Lim, Arijit Raychowdhury. 323-341 [doi]

abstractPIM: A Technology Backward-Compatible Compilation Flow for Processing-In-MemoryAdi Eliahu, Rotem Ben Hur, Ronny Ronen, Shahar Kvatinsky. 343-361 [doi]

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