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    Journal: VLSI Signal Processing

    Volume 19, Issue 3

    215 -- 225Robert Michael Owens, Mohan Vishwanath. A Very Efficient Storage Structure for DWT and IDWT Filters
    227 -- 241Julio Villalba, Tomás Lang, Emilio L. Zapata. Parallel Compensation of Scale Factor for the CORDIC Algorithm
    243 -- 256Yun-Nan Chang, Ching-Yi Wang, Keshab K. Parhi. Heuristic Loop-Based Scheduling and Allocation for DSP Synthesis with Heterogeneous Functional Units
    257 -- 268J. G. Liu, H. F. Li, Francis H. Y. Chan, Francis K. Lam. Fast Discrete Cosine Transform via Computation of Moments
    269 -- 285Chaeryung Park, Taewhan Kim, C. L. Liu. Register Allocation - A Hierarchical Reduction Approach

    Volume 19, Issue 2

    83 -- 0Keshab K. Parhi, Valerie Taylor. Guest Editors Introduction
    85 -- 95Jan Peter Berns, Tobias G. Noll. A Flexible 200 GOPS HDTV Motion Estimation Chip
    97 -- 113Kevin P. Acken, Mary Jane Irwin, Robert Michael Owens. A Parallel ASIC Architecture for Efficient Fractal Image Coding
    115 -- 126Jeffrey D. Hirschberg, David M. Dahle, Kevin Karplus, Don Speck, Richard Hughey. Kestrel: A Programmable Array for Sequence Analysis
    127 -- 147Julio Villalba, Emilio L. Zapata, Elisardo Antelo, Javier D. Bruguera. Radix-4 Vectoring CORDIC Algorithm and Architectures
    167 -- 178Jean-Claude Bajard, Laurent-Stéphane Didier, Jean-Michel Muller. A New Euclidean Division Algorithm for Residue Number Systems
    179 -- 194Philippe Clauss, Vincent Loechner. Parametric Analysis of Polyhedral Iteration Spaces
    195 -- 208Hyuk-Jae Lee, José A. B. Fortes. Automatic Generation of Modular Time-Space Mappings and Data Alignments

    Volume 19, Issue 1

    5 -- 18Alberto Broggi, Gianni Conte, Francesco Gregoretti, Claudio Sansoè, Roberto Passerone, Leonardo Maria Reyneri. Design and Implementation of the PAPRICA Parallel Architecture
    19 -- 38Karl-Heinz Zimmermann, Wolfgang Achtziger. On Time Optimal Implementation of Uniform Recurrences onto Array Processors via Quadratic Programming
    39 -- 50Jaehee You, Sang Uk Lee. High Throughput, Scalable VLSI Architecture for Block Matching Motion Estimation
    51 -- 77Yen-Kuang Chen, S. Y. Kung. A Systolic Design Methodology with Application to Full-Search Block-Matching Architectures
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