| 95 | -- | 96 | Kung Yao. Introduction |
| 97 | -- | 110 | Xiaoxiong Zhong, Sanjay V. Rajopadhye. Quasi-Linear allocation functions for efficient array design |
| 111 | -- | 123 | K. Wojtek Przytula, Viktor K. Prasanna, Wei-Ming Lin. Parallel implementation of neural networks |
| 125 | -- | 145 | Yin-Tsung Hwang, Yu Hen Hu. MSSM - A design aid for multi-stage systolic mapping |
| 147 | -- | 163 | Magdy A. Bayoumi, Padma Rao, Bassem A. Alhalabi. VLSI parallel architecture for Kalman filter::::An algorithm specific approach:::: |
| 165 | -- | 176 | Earl E. Swartzlander Jr., Vijay K. Jain, Hiroomi Hikawa. A radix-8 wafer scale FFT processor |
| 177 | -- | 198 | Hosahalli R. Srinivas, Keshab K. Parhi. High-speed VLSI arithmetic processor architectures using hybrid number representation |
| 199 | -- | 212 | Paul M. Chau, Scott R. Powell. Power dissipation of VLSI array processing systems |
| 213 | -- | 226 | Linda Kwai-Lin Lau, Rajeev Jain, Henry Samueli, Henry T. Nicholas III, Etan G. Cohen. DDFSGEN |
| 227 | -- | 242 | M. Yan, John V. McCanny. Systolic inner product arrays with automatic word rounding |
| 243 | -- | 252 | Mark G. Arnold, Thomas A. Bailey, John R. Cowles, Jerry J. Cupal. Initializing RAM-based logarithmic processors |