Journal: VLSI Signal Processing

Volume 7, Issue 3

189 -- 197John S. Fernando, Milos D. Ercegovac. Conventional and on-line arithmetic designs for high-speed recursive digital filters
199 -- 211Poornachandra B. Rao, Alexander Skavantzos. ROM based methods for computing the squaring operation in modular rings
213 -- 222Vojin G. Oklobdzija, David Villeger, Thierry Soulas. An integrated multiplier for complex numbers
223 -- 232Robert F. Jones, Earl E. Swartzlander Jr.. Parallel counter implementation
233 -- 248Fabian Klass, Michael J. Flynn, A. J. van de Goor. Fast multiplication in VLSI using wave pipelining techniques
249 -- 257Ben C. Drerup, Earl E. Swartzlander Jr.. Fast multiplier bit-product matrix reduction using bit-ordering and parity generation
259 -- 270Paolo Montuschi, Luigi Ciminiera. Radix-8 division with over-redundant digit set
271 -- 285Marianne E. Louie, Milos D. Ercegovac. Implementing division with field programmable gate arrays

Volume 7, Issue 1-2

5 -- 6Teresa H. Y. Meng, Sharad Malik. Editorial
7 -- 16Mark E. Dean, David L. Dill, Mark Horowitz. Self-timed logic using Current-Sensing Completion Detection (CSCD)
17 -- 31Ted E. Williams. Performance of iterative computation in self-timed rings
33 -- 45Ganesh Gopalakrishnan, Venkatesh Akella. High-level optimizations in compiling process descriptions to asynchronous circuits
47 -- 59Erik Brunvand. Designing self-timed systems using concurrent programs
85 -- 100Cho W. Moon, Paul R. Stephan, Robert K. Brayton. Specification, synthesis, and verification of hazard-free asynchronous circuits
101 -- 115Peter Vanbekbergen, Bill Lin, Gert Goossens, Hugo De Man. A generalized state assignment theory for transformations on signal transition graphs
117 -- 135Michael Kishinevsky, Alex Kondratyev, Alexander Taubin. Specification and analysis of self-timed circuits
137 -- 160Luciano Lavagno, Narendra V. Shenoy, Alberto L. Sangiovanni-Vincentelli. Linear programming for hazard elimination in asynchronous circuits
161 -- 182Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert Wang. Verification of asynchronous interface circuits with bounded wire delays