An on-chip testbed that emulates runtime traffic and reduces design verification time for FPGA designs - researchr publication

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Wayne Chen, Lesley Shannon. An on-chip testbed that emulates runtime traffic and reduces design verification time for FPGA designs. In Tarek A. El-Ghazawi, Yao-Wen Chang, Juinn-Dar Huang, Proshanta Saha, editors, 2008 International Conference on Field-Programmable Technology, FPT 2008, Taipei, Taiwan, December 7-10, 2008. pages 361-364, IEEE, 2008. [doi]

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