S. Yoshimoto, T. Amashita, D. Kozuwa, Taiga Takata, M. Yoshimura, Yusuke Matsunaga, H. Yasuura, H. Kawaguchi, M. Yoshimoto. Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structure. In 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 13-15 July, 2011, Athens, Greece. pages 151-156, IEEE, 2011. [doi]
Abstract is missing.