Abstract is missing.
- Modeling and mitigating NBTI in nanoscale circuitsSeyab Khan, Said Hamdioui. 1-6 [doi]
- Investigation of multi cell upset in sequential logic and validity of redundancy techniqueTaiki Uemura, Takashi Kato, Hideya Matsuyama, Keiji Takahisa, Mitsuhiro Fukuda, Kichiji Hatanaka. 7-12 [doi]
- High-level synthesis for multi-cycle transient fault tolerant datapathsTomoo Inoue, Hayato Henmi, Yuki Yoshikawa, Hideyuki Ichihara. 13-18 [doi]
- An intellectual property core to detect task schedulling-related faults in RTOS-based embedded systemsDhiego Silva, Leticia Maria Veiras Bolzani, Fabian Vargas. 19-24 [doi]
- RVC-based time-predictable faulty caches for safety-critical systemsJaume Abella, Eduardo Quiñones, Francisco J. Cazorla, Mateo Valero, Yanos Sazeides. 25-30 [doi]
- Towards functional-safe timing-dependable real-time architecturesMarco Paolieri, Riccardo Mariani. 31-36 [doi]
- Matrix control-flow algorithm-based fault toleranceRonaldo Rodrigues Ferreira, Alvaro Freitas Moreira, Luigi Carro. 37-42 [doi]
- Selective fault tolerance for finite state machinesMichael Augustin, Michael Gössel, Rolf Kraemer. 43-48 [doi]
- A new IP core for fast error detection and fault tolerance in COTS-based solid state mass memoriesEnrico Costenaro, Massimo Violante, Dan Alexandrescu. 49-54 [doi]
- Variability-aware task mapping strategies for many-cores processor chipsFabien Chaix, Gilles Bizot, Michael Nicolaidis, Nacer-Eddine Zergainoh. 55-60 [doi]
- On graceful degradation of microprocessors in presence of faults via resource bankingRance Rodrigues, Sandip Kundu. 61-66 [doi]
- On graceful degradation of chip multiprocessors in presence of faults via flexible pooling of critical execution unitsRance Rodrigues, Sandip Kundu. 67-72 [doi]
- A multi-objective optimization for memory BIST sharing using a genetic algorithmLilia Zaourar, Yann Kieffer, Arnaud Wenzel. 73-78 [doi]
- Memory BIST with address programmabilityAymen Fradi, Michael Nicolaidis, Lorena Anghel. 79-85 [doi]
- Generic BIST architecture for testing of content addressable memoriesH. Grigoryan, G. Harutyunyan, Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian. 86-91 [doi]
- A reliable fault classifier for dependable systems on SRAM-based FPGAsCristiana Bolchini, Chiara Sandionigi, Luca Fossati, David Merodio Codinachs. 92-97 [doi]
- An approach to reduce computational cost in combinatorial logic netlist reliability analysis using circuit clustering and conditional probabilitiesJosep Torras Flaquer, Jean-Marc Daveau, Lirida A. B. Naviner, Philippe Roche. 98-103 [doi]
- Estimation of component criticality in early design stepsMatthias Sauer, Alejandro Czutro, Ilia Polian, Bernd Becker. 104-110 [doi]
- New reliability mechanisms in memory design for sub-22nm technologiesNivard Aymerich, A. Asenov, A. Brown, Ramon Canal, B. Cheng, J. Figueras, Antonio González, Enric Herrero, S. Markov, M. Miranda, P. Pouyan, Tanausu Ramirez, Antonio Rubio, I. Vatajelu, Xavier Vera, X. Wang, P. Zuber. 111-114 [doi]
- A BIST scheme for testing and repair of multi-mode power switchesZhaobo Zhang, Xrysovalantis Kavousianos, Yiorgos Tsiatouhas, Krishnendu Chakrabarty. 115-120 [doi]
- Internal model control for a self-tuning Delay-Locked Loop in UWB communication systemsRshdee Alhakim, Emmanuel Simeu, Kosai Raoof. 121-126 [doi]
- Real time cross-layer adaptation for minimum energy wireless image transport using bit error rate controlJayaram Natarajan, Shreyas Sen, Abhijit Chatterjee. 127-132 [doi]
- The cost of cryptography: Is low budget possible?Ingrid Verbauwhede. 133 [doi]
- Countermeasures against fault attacks: The good, the bad, and the uglyPaolo Maistri. 134-137 [doi]
- Rise of the hardware TrojansBerk Sunar. 138 [doi]
- A novel radiation tolerant SRAM design based on synergetic functional component separation for nanoscale CMOSYuriy Shiyanovskii, Aravind Rajendran, Christos A. Papachristou. 139-144 [doi]
- Noise margin, critical charge and power-delay tradeoffs for SRAM designAravind Rajendran, Yuriy Shiyanovskii, Frank Wolff, Christos A. Papachristou. 145-150 [doi]
- Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structureS. Yoshimoto, T. Amashita, D. Kozuwa, Taiga Takata, M. Yoshimura, Yusuke Matsunaga, H. Yasuura, H. Kawaguchi, M. Yoshimoto. 151-156 [doi]
- Error correction encoding for multi-threshold capture mechanismKedar Karmarkar, Spyros Tragoudas. 157-162 [doi]
- Reduced overhead soft error mitigation using error control coding techniquesV. Prasanth, Virendra Singh, Rubin A. Parekhji. 163-168 [doi]
- Soft error correction in embedded storage elementsMichael E. Imhof, Hans-Joachim Wunderlich. 169-174 [doi]
- A comprehensive soft error analysis methodology for SoCs/ASICs memory instancesDan Alexandrescu. 175-176 [doi]
- A verification strategy for fault-detection and fault-tolerance circuitsGabriele Boschi, Riccardo Mariani, Stefano Lorenzini. 177-178 [doi]
- Accelerating secure circuit design with hardware implementation of Diehard Battery of tests of randomnessAnna Vaskova, Celia López-Ongil, Enrique San Millán, Alejandro Jiménez-Horas, Luis Entrena. 179-181 [doi]
- An FPGA-based framework for run-time injection and analysis of soft errors in microprocessorsM. Sauer, V. Tomashevich, J. Muller, M. Lewis, A. Spilla, I. Polian, B. Becker, W. Burgard. 182-185 [doi]
- An on-line memory state validation using shadow memory cloningMikhail Baklashov. 186-189 [doi]
- Control-flow error recovery using commodity multi-core architecture featuresNavid Khoshavi, Hamid R. Zarandi, Mohammad Maghsoudloo. 190-191 [doi]
- Detection of Trojan HW by using hidden information on the systemOsnat Keren, Ilya Levin, Vladimir Sinelnikov. 192-193 [doi]
- Fault attack resistant deterministic random bit generator usable for key randomizationEberhard Böhl, Paul Duplys. 194-195 [doi]
- Fault-tolerance assessment and enhancement in SoCWire interface: A system-on-chip wireRonak Salamat, Hamid R. Zarandi. 196-197 [doi]
- Generalized parity-check matrices for SEC-DED codes with fixed parityValentin Gherman, Samuel Evain, Nathaniel Seymour, Yannick Bonhomme. 198-201 [doi]
- ICT: Interface software for the characterization and test of mixed-signal power coresJorge O. M. Esteves, Tiago H. Moita, Carlos B. Almeida, Marcelino B. dos Santos. 202-205 [doi]
- Loopback output router for reliable Network on ChipCedric Killian, Camel Tanougast, Fabrice Monteiro, Abbas Dandache. 206-207 [doi]
- Multi-level secure JTAG architectureLuke Pierce, Spyros Tragoudas. 208-209 [doi]
- Self-checking test circuits for latches and flip-flopsRenato P. Ribas, Yuyang Sun, André Inácio Reis, André Ivanov. 210-213 [doi]
- Software-based control flow error detection and correction using branch triplicationNahid Farhady Ghalaty, Mahdi Fazeli, Hossein Izadi Rad, Seyed Ghassem Miremadi. 214-217 [doi]
- Variations of fault manifestation during Burn-In - A case study on industrial SRAM test resultsMichael Linder, Alfred Eder, Klaus Oberlönder, Martin Huch. 218-221 [doi]
- A side channel attack countermeasure using system-on-chip power profile scramblingArmin Krieg, Johannes Grinschgl, Christian Steger, Reinhold Weiss, Josef Haid. 222-227 [doi]
- AKARI-X: A pseudorandom number generator for secure lightweight systemsHonorio Martin, Enrique San Millán, Luis Entrena, Julio César Hernández Castro, Pedro Peris-Lopez. 228-233 [doi]
- Algebraic manipulation detection codes and their applications for design of secure cryptographic devicesZhen Wang, Mark G. Karpovsky. 234-239 [doi]
- Towards improved survivability in safety-critical systemsJaume Abella, Francisco J. Cazorla, Eduardo Quiñones, Arnaud Grasset, Sami Yehia, Philippe Bonnot, Dimitris Gizopoulos, Riccardo Mariani, Guillem Bernat. 240-245 [doi]
- A robust algorithm for pessimistic analysis of logic masking effects in combinational circuitsTaiga Takata, Yusuke Matsunaga. 246-251 [doi]
- An analytical model for the calculation of the Expected Miss Ratio in faulty cachesDaniel Sánchez, Yiannakis Sazeides, Juan L. Aragón, Joso M. Garcia. 252-257 [doi]
- Evaluation techniques for on-line testing of robust systems based on critical tasks distributionAnna Vaskova, Celia López-Ongil, Mario García-Valderas, Marta Portela-García, Luis Entrena. 258-263 [doi]
- Unidirectional error detection, localization and correction for DRAMs: Application to on-line DRAM repair strategiesNeagu Madalin, Liviu Miclea, Joan Figueras. 264-269 [doi]
- An effective methodology for on-line testing of embedded microprocessorsPaolo Bernardi, L. Ciganda, E. Sanchez, Matteo Sonza Reorda. 270-275 [doi]
- Fail-safety in core-based system designRafal Baranowski, Hans-Joachim Wunderlich. 276-281 [doi]