A chip-level path-delay-distribution based Dual-VDD method for low power FPGA (abstract only)

Jianfeng Zhu, Dong Wu, Yaru Yan, Xiao Yu, Hu He, Liyang Pan. A chip-level path-delay-distribution based Dual-VDD method for low power FPGA (abstract only). In John Wawrzynek, Katherine Compton, editors, Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, FPGA 2011, Monterey, California, USA, February 27, March 1, 2011. pages 281, ACM, 2011. [doi]

Abstract

Abstract is missing.