Table of Contents

• Some Real Observations on Virtual MachinesJames E. Smith. 1 [doi]
• Replica Victim Caching to Improve Reliability of In-Cache ReplicationWei Zhang 0002. 2-15 [doi]
• Efficient Victim Mechanism on Sector Cache OrganizationChunrong Lai, Shih-Lien Lu. 16-29 [doi]
• Cache Behavior Analysis of a Compiler-Assisted Cache Replacement PolicyXingyan Tian, Kejia Zhao, Huowang Chen, Hongyan Du. 30-43 [doi]
• Modeling the Cache Behavior of Codes with Arbitrary Data-Dependent Conditional StructuresDiego Andrade, Basilio B. Fraguela, Ramon Doallo. 44-57 [doi]
• A Configurable System-on-Chip Architecture for Embedded DevicesSebastian Wallner. 58-71 [doi]
• An Auto-adaptative Reconfigurable Architecture for the ControlNicolas Ventroux, Stéphane Chevobbe, Frédéric Blanc, Thierry Collette. 72-87 [doi]
• Enhancing the Memory Performance of Embedded Systems with the Flexible Sequential and Random Access MemoryYing Chen, Karthik Ranganathan, Vasudev V. Pai, David J. Lilja, Kia Bazargan. 88-101 [doi]
• Heuristic Algorithm for Reducing Mapping Sets of Hardware-Software Partitioning in Reconfigurable SystemSeong-Yong Ahn, Jun-Yong Kim, Jeong-A. Lee. 102-114 [doi]
• Architecture Design of a High-Performance 32-Bit Fixed-Point DSPJian Chen, Ruhao Xu, Yuzhuo Fu. 115-125 [doi]
• TengYue-1TengYue: In Chinese means jump over.: A High Performance Embedded SoCLei Wang, Hongyi Lu, Kui Dai, Zhiying Wang. 126-136 [doi]
• A Fault-Tolerant Single-Chip MultiprocessorWenbin Yao, Dongsheng Wang, Weimin Zheng. 137-145 [doi]
• Initial Experiences with Dreamy Memory and the RAMpage Memory HierarchyPhilip Machanick. 146-159 [doi]
• dDVS: An Efficient Dynamic Voltage Scaling Algorithm Based on the Differential of CPU UtilizationKui-Yon Mun, Dae Woong Kim, Do-Hun Kim, Chan-Ik Park. 160-169 [doi]
• High Performance Microprocessor Design Methods Exploiting Information Locality and Data Redundancy for Lower Area Cost and Power ConsumptionByung-Soo Choi, Jeong-A. Lee, Dong-Soo Har. 170-184 [doi]
• Dynamic Reallocation of Functional Units in Superscalar ProcessorsMarc Epalza, Paolo Ienne, Daniel Mlynek. 185-198 [doi]
• Multiple-Dimension Scalable Adaptive Stream ArchitectureMei Wen, Nan Wu, Haiyan Li, Chunyuan Zhang. 199-211 [doi]
• Impact of Register-Cache Bandwidth Variation on Processor PerformanceKentaro Hamayasu, Vasily G. Moshnyaga. 212-225 [doi]
• Exploiting Free Execution Slots on EPIC Processors for Efficient and Accurate Runtime ProfilingYoufeng Wu, Yong-Fong Lee. 226-240 [doi]
• Continuous Adaptive Object-Code Re-optimization FrameworkHoward Chen, Jiwei Lu, Wei-Chung Hsu, Pen-Chung Yew. 241-255 [doi]
• Initial Evaluation of a User-Level Device Driver FrameworkKevin Elphinstone, Stefan Götz. 256-269 [doi]
• A Generation Ahead of Microprocessor: Where Software Can Drive uArchitecture To?Jesse Zhixi Fang. 270 [doi]
• A Cost-Effective Supersampling for Full Scene AntiAliasingByung-Uck Kim, Woo-Chan Park, Sung-Bong Yang, Tack-Don Han. 271-281 [doi]
• A Simple Architectural Enhancement for Fast and Flexible Elliptic Curve Cryptography over Binary Finite Fields GF(2:::m:::)Stefan Tillich, Johann Großschädl. 282-295 [doi]
• Scalable Design Framework for JPEG2000 System ArchitectureHiroshi Tsutsui, Takahiko Masuzaki, Yoshiteru Hayashi, Yoshitaka Taki, Tomonori Izumi, Takao Onoye, Yukihiro Nakamura. 296-308 [doi]
• Real-Time Three Dimensional VisionJongSu Yi, JunSeong Kim, LiPing Li, John Morris, Gareth Lee, Philippe Leclercq. 309-320 [doi]
• A Router Architecture for QoS Capable ClustersMadhusudhanan Anantha, Bella Bose. 321-334 [doi]
• Optimal Scheduling Algorithms in WDM Optical Interconnects with Limited Range Wavelength Conversion CapabilityZhenghao Zhang, Yuanyuan Yang. 335-348 [doi]
• Comparative Evaluation of Adaptive and Deterministic Routing in the OTIS-HypercubeHashem Hashemi Najaf-abadi, Hamid Sarbazi-Azad. 349-362 [doi]
• A Two-Level On-Chip Bus System Based on MultiplexersKyoung-Sun Jhang, Kang Yi, Soo Yun Hwang. 363-372 [doi]
• Make Computers Cheaper and SimplerGuojie Li. 373 [doi]
• A Low Power Branch Predictor to Selectively Access the BTBSung Woo Chung, Sung-Bae Park. 374-384 [doi]
• Static Techniques to Improve Power Efficiency of Branch PredictorsWeidong Shi, Tao Zhang, Santosh Pande. 385-398 [doi]
• Choice Predictor for FreeMongkol Ekpanyapong, Pinar Korkmaz, Hsien-Hsin S. Lee. 399-413 [doi]
• Performance Impact of Different Data Value PredictorsYong Xiao, Kun Deng, Xingming Zhou. 414-425 [doi]
• Heterogeneous Networks of WorkstationsSunHo Baek, KyuHo Lee, JunSeong Kim, John Morris. 426-439 [doi]
• Finding High Performance Solution in Reconfigurable Mesh-Connected VLSI ArraysWu Jigang, Thambipillai Srikanthan. 440-448 [doi]
• Order Independent Transparency for Image Composition Parallel Rendering MachinesWoo-Chan Park, Tack-Don Han, Sung-Bong Yang. 449-460 [doi]
• An Authorization Architecture Oriented to Engineering and Scientific Computation in Grid EnvironmentsChangqin Huang, Guanghua Song, Yao Zheng, Deren Chen. 461-472 [doi]
• Validating Word-Oriented Processors for Bit and Multi-word OperationsRuby B. Lee, Xiao Yang, Zhijie Shi. 473-488 [doi]
• Dynamic Fetch Engine for Simultaneous Multithreaded ProcessorsTzung-Rei Yang, Jong-Jiann Shieh. 489-502 [doi]
• A Novel Rename Register Architecture and Performance AnalysisZhenyu Liu, Jiayue Qi. 503-514 [doi]
• A New Hierarchy Cache Scheme Using RAM and PagefileRui-fang Liu, Change-sheng Xie, Zhi-hu Tan, Qing Yang. 515-526 [doi]
• An Object-Oriented Data Storage System on Network-Attached Object DevicesYouhui Zhang, Weimin Zheng. 527-538 [doi]
• A Scalable and Adaptive Directory Scheme for Hardware Distributed Shared MemoryKiyofumi Tanaka, Toshihide Hagiwara. 539-553 [doi]
• A Compiler-Assisted On-Chip Assigned-Signature Control Flow CheckingXiaobin Li, Jean-Luc Gaudiot. 554-567 [doi]
• A Floating Point Divider Performing IEEE Rounding and Quotient Conversion in ParallelWoo-Chan Park, Tack-Don Han, Sung-Bong Yang. 568-581 [doi]
• Efficient Buffer Allocation for Asynchronous Linear Pipelines by Design Space LocalizationJeong-Gun Lee, Euiseok Kim, Jeong-A. Lee, Eunok Paek. 582-595 [doi]