Abstract is missing.
- Architectural Exploration of the ADRES Coarse-Grained Reconfigurable ArrayFrank Bouwens, Mladen Berekovic, Andreas Kanstein, Georgi Gaydadjiev. 1-13 [doi]
- A Configurable Multi-ported Register File Architecture for Soft Processor CoresMazen A. R. Saghir, Rawan Naous. 14-25 [doi]
- MT-ADRES: Multithreading on Coarse-Grained Reconfigurable ArchitectureKehuai Wu, Andreas Kanstein, Jan Madsen, Mladen Berekovic. 26-38 [doi]
- Asynchronous ARM Processor Employing an Adaptive Pipeline ArchitectureJe-Hoon Lee, Seung-Sook Lee, Kyoung-Rok Cho. 39-48 [doi]
- Partially Reconfigurable Point-to-Point Interconnects in Virtex-II Pro FPGAsJae Young Hur, Stephan Wong, Stamatis Vassiliadis. 49-60 [doi]
- Systematic Customization of On-Chip Crossbar InterconnectsJae Young Hur, Todor Stefanov, Stephan Wong, Stamatis Vassiliadis. 61-72 [doi]
- Authentication of FPGA Bitstreams: Why and HowSaar Drimer. 73-84 [doi]
- Design of a Reversible PLD ArchitectureJae-Jin Lee, Dong-Guk Hwang, Gi-Yong Song. 85-90 [doi]
- Designing Heterogeneous FPGAs with Multiple SBsKostas Siozios, Stelios Mamagkakis, Dimitrios Soudris, Antonios Thanailakis. 91-96 [doi]
- Partial Data Reuse for Windowing Computations: Performance Modeling for FPGA ImplementationsJoonseok Park, Pedro C. Diniz. 97-109 [doi]
- Optimized Generation of Memory Structure in Compiling Window Operations onto Reconfigurable HardwareYazhuo Dong, Yong Dou, Jie Zhou. 110-121 [doi]
- Adapting and Automating XILINX s Partial Reconfiguration Flow for Multiple Module ImplementationsRainer Scholz. 122-129 [doi]
- A Linear Complexity Algorithm for the Automatic Generation of Convex Multiple Input Multiple Output InstructionsCarlo Galuzzi, Koen Bertels, Stamatis Vassiliadis. 130-141 [doi]
- Evaluating Variable-Grain Logic Cells Using Heterogeneous Technology MappingKazunori Matsuyama, Motoki Amagasaki, Hideaki Nakayama, Ryoichi Yamaguchi, Masahiro Iida, Toshinori Sueyoshi. 142-154 [doi]
- The Implementation of a Coarse-Grained Reconfigurable Architecture with Loop Self-pipeliningYong Dou, Jinhui Xu, Guiming Wu. 155-166 [doi]
- Hardware/Software Codesign for Embedded Implementation of Neural NetworksCesar Torres-Huitzil, Bernard Girau, Adrien Gauffriau. 167-178 [doi]
- Synthesis of Regular Expressions Targeting FPGAs: Current Status and Open IssuesJoão Bispo, Ioannis Sourdis, João M. P. Cardoso, Stamatis Vassiliadis. 179-190 [doi]
- About the Importance of Operation Grouping Procedures for Multiple Word-Length Architecture OptimizationsNicolas Hervé, Daniel Menard, Olivier Sentieys. 191-200 [doi]
- Switching Activity Models for Power Estimation in FPGA MultipliersRuzica Jevtic, Carlos Carreras, Gabriel Caffarena. 201-213 [doi]
- Multiplication over F::p:::m::::: on FPGA: A SurveyJean-Luc Beuchat, Takanori Miyoshi, Yoshihito Oyama, Eiji Okamoto. 214-225 [doi]
- A Parallel Version of the Itoh-Tsujii Multiplicative Inversion AlgorithmFrancisco Rodríguez-Henríquez, Guillermo Morales-Luna, Nazar A. Saqib, Nareli Cruz Cortés. 226-237 [doi]
- A Fast Finite Field MultiplierEdgar Ferrer, Dorothy Bollman, Oscar Moreno. 238-246 [doi]
- Combining Flash Memory and FPGAs to Efficiently Implement a Massively Parallel Algorithm for Content-Based Image RetrievalRayan Chikhi, Steven Derrien, Auguste Noumsi, Patrice Quinton. 247-258 [doi]
- Image Processing Architecture for Local Features ComputationJavier Díaz, Eduardo Ros, Sonia Mota, Richard R. Carrillo. 259-270 [doi]
- A Compact Shader for FPGA-Based Volume Rendering AcceleratorsGünter Knittel. 271-282 [doi]
- Ubiquitous Evolvable Hardware System for Heart Disease Diagnosis ApplicationsYong-Min Lee, Chang-Seok Choi, Seung-Gon Hwang, Hyun Dong Kim, Chul Hong Min, Jae-Hyun Park, Hanho Lee, Tae-Seon Kim, Chong-Ho Lee. 283-292 [doi]
- FPGA-Accelerated Molecular Dynamics Simulations: An OverviewXiaodong Yang, Shengmei Mou, Yong Dou. 293-301 [doi]
- Reconfigurable Hardware Acceleration of Canonical Graph LabellingDavid B. Thomas, Wayne Luk, Michael Stumpf. 302-313 [doi]
- Reconfigurable Computing for Accelerating Protein Folding SimulationsNilton B. Armstrong, Heitor S. Lopes, Carlos R. Erig Lima. 314-325 [doi]
- Reconfigurable Parallel Architecture for Genetic Algorithms: Application to the Synthesis of Digital CircuitsEdson P. Ferlin, Heitor S. Lopes, Carlos R. Erig Lima, Ederson Cichaczewski. 326-336 [doi]
- A Space Variant Mapping Architecture for Reliable Car SegmentationSonia Mota, Eduardo Ros, Javier Díaz, Rafael Rodríguez-Gomez, Richard R. Carrillo. 337-342 [doi]
- A Hardware SAT Solver Using Non-chronological Backtracking and Clause Recording Without OverheadsShinya Hiramoto, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima. 343-349 [doi]
- Searching the Web with an FPGA Based Search EngineSéamas McGettrick, Dermot Geraghty, Ciarán McElroy. 350-357 [doi]
- An Acceleration Method for Evolutionary Systems Based on Iterated Prisoner s DilemmaYoshiki Yamaguchi, Kenji Kanazawa, Yoshiharu Ohke, Tsutomu Maruyama. 358-364 [doi]
- Real Time Architectures for Moving-Objects TrackingMatteo Tomasi, Javier Díaz, Eduardo Ros. 365-372 [doi]
- Reconfigurable Hardware Evolution Platform for a Spiking Neural Network Robotics ControllerPatrick Rocke, Brian McGinley, Fearghal Morgan, John Maher. 373-378 [doi]
- Multiple Sequence Alignment Using Reconfigurable ComputingCarlos R. Erig Lima, Heitor S. Lopes, Maiko R. Moroz, Ramon M. Menezes. 379-384 [doi]
- Simulation of the Dynamic Behavior of One-Dimensional Cellular Automata Using Reconfigurable ComputingWagner R. Weinert, César Benitez, Heitor S. Lopes, Carlos R. Erig Lima. 385-390 [doi]