Abstract is missing.
- Computer Arithmetic-A Processor Architect s PerspectiveRuby B. Lee. 3 [doi]
- Leading Zero Anticipation and Detection-A Comparison of MethodsMartin S. Schmookler, Kevin J. Nowka. 7-12 [doi]
- Bounds on Runs of Zeros and Ones for Algebraic FunctionsTomás Lang, Jean-Michel Muller. 13 [doi]
- Binary Multiplication Radix-32 and Radix-256Peter-Michael Seidel, Lee D. McFearin, David W. Matula. 23-32 [doi]
- Analysis of Column Compression MultipliersK Andrea C. Bickerstaff, Earl E. Swartzlander Jr., Michael J. Schulte. 33-39 [doi]
- Faithful Powering Computation Using Table Look-Up and a Fused Accumulation TreeJosé-Alejandro Piñeiro, Javier D. Bruguera, Jean-Michel Muller. 40 [doi]
- Modular Multiplication and Base Extensions in Residue Number SystemsJean-Claude Bajard, Laurent-Stéphane Didier, Peter Kornerup. 59-65 [doi]
- Efficient Computation of Multiplicative Inverses for Cryptographic ApplicationsM. Anwarul Hasan. 66-72 [doi]
- Optimised Squaring of Long Integers Using Precomputed Partial ProductsBraden Phillips. 73 [doi]
- Correctly Rounded Reciprocal Square-Root by Digit Recurrence and Radix-4 ImplementationTomás Lang, Elisardo Antelo. 83-93 [doi]
- A Hardware Algorithm for Computing Reciprocal Square RootNaofumi Takagi. 94-100 [doi]
- Improved Table Lookup Algorithms for Postscaled DivisionDavid W. Matula. 101 [doi]
- Worst Cases for Correct Rounding of the Elementary Functions in Double PrecisionVincent Lefèvre, Jean-Michel Muller. 111-118 [doi]
- Generation and Analysis of Hard to Round Cases for Binary Floating Point DivisionLee D. McFearin, David W. Matula. 119-127 [doi]
- Some Improvements on Multipartite Table Methods Florent de Dinechin, Arnaud Tisserand. 128-135 [doi]
- High-Performance Architectures for Elementary Function GenerationJun Cao, Belle W. Y. Wei, Jie Cheng. 136 [doi]
- A Decimal Floating-Point SpecificationMichael F. Cowlishaw, Eric M. Schwarz, Ronald M. Smith, Charles F. Webb. 147-154 [doi]
- Algorithms for Quad-Double Precision Floating Point ArithmeticYozo Hida, Xiaoye S. Li, David H. Bailey. 155-162 [doi]
- Effective Continued FractionsDavid Lester. 163 [doi]
- 1-GHz HAL SPARC64 Dual Floating Point Unit with RAS FeaturesAjay Naini, Atul Dhablania, Warren James, Debjit Das Sarma. 173-183 [doi]
- On the Design of Fast IEEE Floating-Point AddersPeter-Michael Seidel, Guy Even. 184-194 [doi]
- In-Order Issue Out-of-Order Execution Floating-Point Coprocessor for CalmRISC32Cheol-Ho Jeong, Woo-Chan Park, Tack-Don Han, Moon Key Lee, Sang-Woo Kim. 195 [doi]
- Using the Reverse-Carry Approach for Double Datapath Floating-Point AdditionJavier D. Bruguera, Tomás Lang. 203-210 [doi]
- High Speed Parallel-Prefix Modulo 2n+1 Adders for Diminished-One OperandsHaridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou. 211-217 [doi]
- Parallel Prefix Adder DesignAndrew Beaumont-Smith, Cheng-Chew Lim. 218 [doi]
- Low-Power Properties of the Logarithmic Number SystemVassilis Paliouras, Thanos Stouraitis. 229-236 [doi]
- Unrestricted Faithful Rounding is Good Enough for Some LNS ApplicationsMark G. Arnold, Colin D. Walter. 237-246 [doi]
- The Use of the Multi-Dimensional Logarithmic Number System in DSP ApplicationsVassil S. Dimitrov, Jonathan Eskritt, Laurent Imbert, Graham A. Jullien, William C. Miller. 247 [doi]
- On-line Arithmetic for Detection in Digital Communication ReceiversSridhar Rajagopal, Joseph R. Cavallaro. 257-265 [doi]
- A Design of Radix-2 On-line Division Using LSA OrganizationAlexandre F. Tenca, Syed Ubaid Hussaini. 266 [doi]
- A Family of AddersSimon Knowles. 277 [doi]