Abstract is missing.
- The naive execution of affine recurrence equationsDoran Wilde, Sanjay V. Rajopadhye. 1-12 [doi]
- Revisiting the Decomposition of Karp, Miller and WinogradAlain Darte, Frédéric Vivien. 13-25 [doi]
- A Processor-Time-Minimal Schedule for 3D Rectilinear Mesh AlgorithmsChris J. Scheiman, Peter R. Cappello. 26-33 [doi]
- Data Alignments for Modular Time-Space Mappings of BLAS-like AlgorithmsHyuk-Jae Lee, José A. B. Fortes. 34 [doi]
- Time-optimal ranking algorithms on sorted matricesVenkatavasu Bokka, Himabindu Gurla, Stephan Olariu, James L. Schwing, Larry Wilson. 42-53 [doi]
- Recomputing by Operand Exchanging: A Time-redundancy Approach for Fault-tolerant Neural NetworksYuang-Ming Hsu, Earl E. Swartzlander Jr., Vincenzo Piuri. 54-65 [doi]
- Design and Implementation of a Parallel Image Processor Chip for a SIMD Array ProcessorMyung Hoon Sunwoo, Soohwan Ong, Byungdug Ahn, Kyungwoo Lee. 66-75 [doi]
- A Scalable Halftoning Coprocessor ArchitectureAnders Kugler, Roger D. Hersch. 76-84 [doi]
- Horizontal Microcode Compaction for Programmable Systolic AcceleratorsPaolo Ienne. 85 [doi]
- Column Compression Pipelined MultipliersLuca Breveglieri, Luigi Dadda, Vincenzo Piuri. 93-103 [doi]
- A Processor for Staggered Interval ArithmeticMichael J. Schulte, Earl E. Swartzlander Jr.. 104-112 [doi]
- A simple array processor for binary prefix sumsRong Lin, Stephan Olariu. 113 [doi]
- The MGAP s programming environment and the *C++ languageRaminder Singh Bajwa, Robert Michael Owens, Mary Jane Irwin. 121-124 [doi]
- The VLSI design and implementation of the array processors of a multilayer vision system architectureB. Saha, J. Sukarno Mertoguno, Nikolaos G. Bourbakis. 125-128 [doi]
- A Parallelizing Compilation Method for the Map-oriented MachineReiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig, Karin Schmidt. 129-132 [doi]
- VLSI Algorithms for Compressed Pattern Search Using Tree Based CodesAmar Mukherjee, Tinku Acharya. 133-136 [doi]
- Parallel Sequence Comparison and AlignmentRichard Hughey. 137-140 [doi]
- The Systolic Design of a Block Regularised Parameter Estimator using Hierarchical Signal Flow GraphsD. W. Brown, F. M. F. Gaston. 141 [doi]
- Systolic Filter for Fast DNA Similarity SearchPascale Guerdoux-Jamet, Dominique Lavenier. 145-156 [doi]
- A Solid Translation Engine using Ray RepresentationThomas Alexander, John L. Ellis, Gershon Kedem. 157-165 [doi]
- Input buffering requirements of a Systolic Array for the Inverse Discrete Wavelet TransformRobert Lang, Andrew Spray. 166-173 [doi]
- Synthesis of VLSI Architectures for Two-Dimensional Discrete Wavelet TransformsJongwoo Bae, Viktor K. Prasanna. 174 [doi]
- Parallel Implementation of the Full Search Block Matching Algorithm for Motion EstimationPierpaolo Baglietto, Massimo Maresca, A. Migliaro, Mauro Migliardi. 182-192 [doi]
- MOVIE: A Building Block for the Design of Real Time Simulator of Moving Pictures Compression AlgorithmsRonan Barzic, Christian Bouville, François Charot, Gwendal Le Fol, Pascal Lemonnier, Charles Wagner. 193-203 [doi]
- Motion Estimation Algorithms on Fine Grain Array ProcessorHeung-Nam Kim, Mary Jane Irwin, Robert Michael Owens. 204-213 [doi]
- Bit Level Block Matching Systolic ArraysYin Chan, Sun-Yuan Kung. 214 [doi]
- Techniques for Yield Enhancement of VLSI AddersZhan Chen, Israel Koren. 222-229 [doi]
- Interfacing FPGA/VLSI Processor ArraysJoseph A. Fernando, Jack S. N. Jean. 230-237 [doi]
- Implementation of Parallel Arithmetic in a Cellular AutomatonRichard K. Squier, Kenneth Steiglitz, Mariusz H. Jakubowski. 238 [doi]
- Digit On-line Large Radix CORDIC RotatorRoberto R. Osorio, Elisardo Antelo, Javier D. Bruguera, Julio Villalba, Emilio L. Zapata. 246-257 [doi]
- CORDIC Architectures with Parallel Compensation of the Scale FactorJulio Villalba, J. A. Hidalgo, Emilio L. Zapata, Elisardo Antelo, Javier D. Bruguera. 258-269 [doi]
- An array processor for inner product computations using a Fermat number ALUWenzhe Luo, Graham A. Jullien, Neil M. Wigley, William C. Miller, Zhongde Wang. 270-281 [doi]
- Design of a systolic coprocessor for rational additionTudor Jebelean. 282-289 [doi]
- Multilayer Cellular Algorithm for Complex Number MultiplicationValentina P. Markova. 290 [doi]
- Minimizing Synchronization Overhead in Statically Scheduled Multiprocessor SystemsShuvra S. Bhattacharyya, Sundararajan Sriram, Edward A. Lee. 298-309 [doi]
- Synthesis of Multirate VLSI ArraysPatrick M. Lenders, Sanjay V. Rajopadhye. 310-321 [doi]
- A Design Tool for the Specification and the Simulation of Array Processors Architectures - Application to Image Processing: The Extraction of Regions of InterestsGérard Ramstein, Olivier Déforges, P. Bakowski. 322-329 [doi]
- Precise Tiling for Uniform Loop NestsPierre-Yves Calland, Tanguy Risset. 330 [doi]