Abstract is missing.
- Wireless innovations for smartphonesHannu Kauppinen. 1-2 [doi]
- Computing without processorsSatnam Singh. 3-4 [doi]
- A standards-based, fully-open software platform for smart embedded systemsJong-Deok Choi. 5-6 [doi]
- Internet-of-energy: combining embedded computing and communication for the smart gridRandolf Mock, Moritz Neukirchner, Rolf Ernst, Ruud Wijtvliet, Michael Huetwohl, Pascal Urard, Ovidiu Vermesan. 7-8 [doi]
- Trends in automotive embedded systemsDan Gunnarsson, Stefan Kuntz, Glenn Farrall, Akihito Iwai, Rolf Ernst. 9-10 [doi]
- Research issues in smart phones, notepads and related servicesPetri Liuha, Kari Pehkonen, Juhani Rummukainen, Veli-Pekka Vatula, Tatu Koljonen. 11-12 [doi]
- Lifetime improvement through runtime wear-based task mappingAdam S. Hartman, Donald E. Thomas. 13-22 [doi]
- A real-time, energy-efficient system software suite for heterogeneous multicore platformsShih-Hao Hung, Chi-Sheng Shih, Tei-Wei Kuo, Chia-Heng Tu, Che-Wei Chang. 23-32 [doi]
- ViPZonE: OS-level memory variability-driven physical address zoning for energy savingsLuis Angel D. Bathen, Mark Gottscho, Nikil Dutt, Alex Nicolau, Puneet Gupta. 33-42 [doi]
- Dynamic transient fault detection and recovery for embedded processor datapathsGaro Bournoutian, Alex Orailoglu. 43-52 [doi]
- SPI-SNOOPER: a hardware-software approach for transparent network monitoring in wireless sensor networksMohammad Sajjad Hossain, Woo Suk Lee, Vijay Raghunathan. 53-62 [doi]
- A novel NoC-based design for fault-tolerance of last-level caches in CMPsAbbas BanaiyanMofrad, Gustavo Girão, Nikil Dutt. 63-72 [doi]
- Automatic extraction of multi-objective aware pipeline parallelism using genetic algorithmsDaniel Cordes, Michael Engel, Peter Marwedel, Olaf Neugebauer. 73-82 [doi]
- Managing latency in embedded streaming applications under hard-real-time schedulingMohamed Bamakhrama, Todor Stefanov. 83-92 [doi]
- Dynamic scheduling of stream programs on embedded multi-core processorsHaeseung Lee, Weijia Che, Karam S. Chatha. 93-102 [doi]
- A distributed interleaving scheme for efficient access to WideIO DRAM memoryCiprian Seiculescu, Luca Benini, Giovanni De Micheli. 103-112 [doi]
- Minimizing power supply noise through harmonic mappings in networks-on-chipNizar Dahir, Terrence S. T. Mak, Fei Xia, Alex Yakovlev. 113-122 [doi]
- Worst-case performance analysis of 2-D mesh NoCs using multi-path minimal routingGaoming Du, Cunqiang Zhang, Zhonghai Lu, Alberto Saggio, Minglun Gao. 123-132 [doi]
- HyCoS: hybrid compiled simulation of embedded software with target dependent codeZhonglei Wang, Jörg Henkel. 133-142 [doi]
- Fast simulation of systems embedding VLIW processorsLuc Michel, Nicolas Fournel, Frédéric Pétrot. 143-150 [doi]
- DIMSim: a rapid two-level cache simulation approach for deadline-based MPSoCsMohammad Shihabul Haque, Roshan G. Ragel, Jude Angelo Ambrose, Swarnalatha Radhakrishnan, Sri Parameswaran. 151-160 [doi]
- A traffic-aware adaptive routing algorithm on a highly reconfigurable network-on-chip architectureZhiliang Qian, Paul Bogdan, Guopeng Wei, Chi-Ying Tsui, Radu Marculescu. 161-170 [doi]
- The roce-bush router: a case for routing-centric dimensional decomposition for low-latency 3D noC routersMiguel Salas, Sudeep Pasricha. 171-180 [doi]
- Non-intrusive trace & debug noc architecture with accurate timestamping for GALS SoCsVladimir Todorov, Alberto Ghiribaldi, Helmut Reinig, Davide Bertozzi, Ulf Schlichtmann. 181-186 [doi]
- Dynamic property mining for embedded softwareMarco Bonato, Giuseppe Di Guglielmo, Masahiro Fujita, Franco Fummi, Graziano Pravadelli. 187-196 [doi]
- Efficient self-learning techniques for SAT-based test generationAng Li, Mingsong Chen. 197-206 [doi]
- Using static analysis for coverage extraction fromemulation/prototyping platformsViraj Athavale, Sam Hertz, Darshan Jetly, Vijay Ganesan, Jim Krysl, Shobha Vasudevan. 207-214 [doi]
- Synthesis of custom networks of heterogeneous processing elements for complex physical system emulationChen Huang, Bailey Miller, Frank Vahid, Tony Givargis. 215-224 [doi]
- Knowledge-based design space exploration of wireless sensor networksPaolo Roberto Grassi, Ivan Beretta, Vincenzo Rana, David Atienza, Donatella Sciuto. 225-234 [doi]
- Spatially- and temporally-adaptive communication protocols for zero-maintenance sensor networks relying on opportunistic energy scavengingXuejing He, Robert P. Dick, Russ Joseph. 235-244 [doi]
- Performance enhancement under power constraints using heterogeneous CMOS-TFET multicoresEmre Kultursay, Karthik Swaminathan, Vinay Saripalli, Vijaykrishnan Narayanan, Mahmut T. Kandemir, Suman Datta. 245-254 [doi]
- COOL: control-based optimization of load-balancing for thermal behaviorThomas Ebi, Hussam Amrouch, Jörg Henkel. 255-264 [doi]
- Adaptive online heuristic performance estimation and power optimization for reconfigurable embedded systemsJingqing Mu, Roman L. Lysecky. 265-274 [doi]
- BPR: fast FPGA placement and routing using macroblocksJames Coole, Greg Stitt. 275-284 [doi]
- Generating interlocked instruction pipelines from specifications of instruction setsRalf Dreesen. 285-294 [doi]
- Designing parameterized signal processing ips for high level synthesis in a model based design environmentShahzad Ahmad Butt, Luciano Lavagno. 295-304 [doi]
- Testbenches for advanced TLM verificationWolfgang Müller 0003, Wolfgang Ecker. 305-306 [doi]
- SystemC as completing pillar in industrial OVM based verification environmentsWolfgang Ecker, Volkan Esen, Michael Velten, Tudor Timisescu. 307-312 [doi]
- The system verification methodology for advanced TLM verificationMarcio F. da S. Oliveira, Christoph Kuznik, Hoang M. Le, Daniel Große, Finn Haedicke, Wolfgang Müller 0003, Rolf Drechsler, Wolfgang Ecker, Volkan Esen. 313-322 [doi]
- Generation of TLM testbenches using mutation testingMarcelo Sousa, Alper Sen. 323-332 [doi]
- A testbench specification language for SystemC verificationGiuseppe Di Guglielmo, Graziano Pravadelli. 333-342 [doi]
- SystemC simulation on GP-GPUs: CUDA vs. OpenCLNicola Bombieri, Sara Vinco, Valeria Bertacco, Debapriya Chatterjee. 343-352 [doi]
- DevScope: a nonintrusive and online power analysis tool for smartphone hardware componentsWonwoo Jung, Chulkoo Kang, Chanmin Yoon, Dongwon Kim, Hojung Cha. 353-362 [doi]
- ADEL: an automatic detector of energy leaks for smartphone applicationsLide Zhang, Mark S. Gordon, Robert P. Dick, Zhuoqing Morley Mao, Peter A. Dinda, Lei Yang. 363-372 [doi]
- Don't burn your mobile!: safe computational re-sprinting via model predictive controlAndrea Tilli, Andrea Bartolini, Matteo Cacciari, Luca Benini. 373-382 [doi]
- Concurrent architecture and schedule optimization of time-triggered automotive systemsMartin Lukasiewycz, Samarjit Chakraborty. 383-392 [doi]
- A SAFE approach towards early design space exploration of fault-tolerant multimedia MPSoCsPeter van Stralen, Andy D. Pimentel. 393-402 [doi]
- Synthesis of optimized hardware transactors from abstract communication specificationsDongwook Lee, Hyungman Park, Andreas Gerstlauer. 403-412 [doi]
- Fast online synthesis of generally programmable digital microfluidic biochipsDaniel Grissom, Philip Brisk. 413-422 [doi]
- An intelligent compaction technique for pin constrained routing in cross referencing digital microfluidic biochipsPranab Roy, Rupam Bhattacharjee, Modud Sohid, Sudipta Chakraborty, Hafizur Rahaman, Parthasarathi Dasgupta. 423-432 [doi]
- Enabling ultra-low power operation in high-end wireless sensor networks nodesCarlo Brandolese, William Fornaciari, Luigi Rucco, Federico Terraneo. 433-442 [doi]
- Reducing NBTI-induced processor wearout by exploiting the timing slack of instructionsFabian Oboril, Farshad Firouzi, Saman Kiamehr, Mehdi Baradaran Tahoori. 443-452 [doi]
- LRCG: latch-based random clock-gating for preventing power analysis side-channel attacksKazuyuki Tanimura, Nikil D. Dutt. 453-462 [doi]
- Worst-case throughput analysis of real-time dynamic streaming applicationsFirew Siyoum, Marc Geilen, Orlando Moreira, Henk Corporaal. 463-472 [doi]
- Synthesis of communication schedules for TTEthernet-based mixed-criticality systemsDomitian Tamas-Selicean, Paul Pop, Wilfried Steiner. 473-482 [doi]
- A hierarchical control scheme for energy quota distribution in hybrid distributed video codingMuhammad Usman Karim Khan, Muhammad Shafique, Jörg Henkel. 483-492 [doi]
- Working-set-based address mapping for ultra-large-scaled flash devicesMing-Chang Yang, Yuan-Hao Chang, Po-Chun Huang, Tei-Wei Kuo. 493-502 [doi]
- An exploration methodology for a customizable OpenCL stereo-matching application targeted to an industrial multi-cluster architectureEdoardo Paone, Gianluca Palermo, Vittorio Zaccaria, Cristina Silvano, Diego Melpignano, Germain Haugou, Thierry Lepley. 503-512 [doi]
- A case of system-level hardware/software co-design and co-verification of a commodity multi-processor system with custom hardwareSungpack Hong, Tayo Oguntebi, Jared Casper, Nathan Grasso Bronson, Christos Kozyrakis, Kunle Olukotun. 513-520 [doi]
- A configurable test infrastructure using a mixed-language and mixed-level IP integration IP-XACT flowErwin de Kock, Jos Verhaegh, Serge Amougou. 521-528 [doi]
- A MDD methodology for specification of embedded systems and automatic generation of fast configurable and executable performance modelsFernando Herrera, Hector Posadas, Pablo Peñil, Eugenio Villar, Francisco Ferrero, Raúl Valencia. 529-538 [doi]
- Software energy optimization through fine-grained function-level voltage and frequency scalingCarlo Brandolese, William Fornaciari. 539-546 [doi]
- From RTL IP to functional system-level models with extra-functional propertiesDaniel Lorenz, Kim Grüttner, Nicola Bombieri, Valerio Guarnieri, Sara Bocchio. 547-556 [doi]
- Run-time resource management based on design space explorationChantal Ykman-Couvreur, Philipp A. Hartmann, Gianluca Palermo, Fabien Colas-Bigey, Laurent San. 557-566 [doi]
- Network-aware design-space exploration of a power-efficient embedded applicationParinaz Sayyah, Mihai T. Lazarescu, Davide Quaglia, Emad Samuel Malki Ebeid, Sara Bocchio, Alberto Rosti. 567-574 [doi]
- Hands-on tutorial: coarse-grained reconfigurable architectures - compilation and explorationTom Vander Aa, Panagiotis Theocharis. 575-576 [doi]
- Soft errors: the hardware-software interfaceKyoungwoo Lee, Aviral Shrivastava, Reiley Jeyapaul. 577-578 [doi]