Table of Contents

• Conference Organizers [doi]
• Efficient Hardware Data Mining with the Apriori Algorithm on FPGAsZachary K. Baker, Viktor K. Prasanna. 3-12 [doi]
• A Novel 2D Filter Design Methodology for Heterogeneous DevicesChristos-Savvas Bouganis, George A. Constantinides, Peter Y. K. Cheung. 13-22 [doi]
• Prototyping Architectural Support for Program Rollback Using FPGAsRadu Teodorescu, Josep Torrellas. 23-32 [doi]
• Register File Architecture Optimization in a Coarse-Grained Reconfigurable ArchitectureZion Kwok, Steven J. E. Wilton. 35-44 [doi]
• Handling Different Computational Granularity by a Reconfigurable IC Featuring Embedded FPGAs and a Network-on-ChipFrancesco Lertora, Michele Borgatti. 45-54 [doi]
• A Study of the Scalability of On-Chip Routing for Just-in-Time FPGA CompilationRoman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan. 57-62 [doi]
• Simplifying the Integration of Processing Elements in Computing Systems Using a Programmable ControllerLesley Shannon, Paul Chow. 63-72 [doi]
• Evaluation of Code Generation Strategies for Scalar Replaced Codes in Fine-Grain Configurable ArchitecturesPedro C. Diniz. 73-82 [doi]
• FPGA Particle Graphics HardwareJohn Sachs Beeckler, Warren J. Gross. 85-94 [doi]
• Reconfigurable Designs for RadiosityPaul Baker, Tim Todman, Henry Styles, Wayne Luk. 95-104 [doi]
• Hardware Factorization Based on Elliptic Curve MethodMartin Simka, Jan Pelzl, Thorsten Kleinjung, Jens Franke, Christine Priplata, Colin Stahlke, Milos Drutarovský, Viktor Fischer. 107-116 [doi]
• Metropolitan Road Traffic Simulation on FPGAsJustin L. Tripp, Henning S. Mortveit, Anders A. Hansson, Maya Gokhale. 117-126 [doi]
• Time Domain Numerical Simulation for Transient Waves on Reconfigurable Coprocessor PlatformHe Chuan, Wei Zhao, Mi Lu. 127-136 [doi]
• COMA: A COoperative MAnagement Scheme for Energy Efficient Implementation of Real-Time Operating Systems on FPGA Based Soft ProcessorsJingzhao Ou, Viktor K. Prasanna. 139-148 [doi]
• An Execution Environment for Reconfigurable ComputingWenyin Fu, Katherine Compton. 149-158 [doi]
• Higher Radix Floating-Point Representations for FPGA-Based ArithmeticBryan C. Catanzaro, Brent E. Nelson. 161-170 [doi]
• An Analysis of the Double-Precision Floating-Point FFT on FPGAsK. Scott Hemmert, Keith D. Underwood. 171-180 [doi]
• A Comparison of Floating Point and Logarithmic Number Systems for FPGAsMichael Haselman, Michael J. Beauchamp, Aaron Wood, Scott Hauck, Keith D. Underwood, K. Scott Hemmert. 181-190 [doi]
• Terrestrial-Based Radiation Upsets: A Cautionary TaleHeather Quinn, Paul Graham. 193-202 [doi]
• Automating the Layout of Reconfigurable Subsystems Using Circuit GeneratorsShawn Phillips, Scott Hauck. 203-212 [doi]
• Fast Reconfiguring Deep Packet Filter for 1+ Gigabit NetworkYoung H. Cho, William H. Mangione-Smith. 215-224 [doi]
• A Framework for Rule Processing in Reconfigurable Network SystemsMichael Attig, John W. Lockwood. 225-234 [doi]
• A Signature Match Processor Architecture for Network Intrusion DetectionJanardhan Singaraju, Long Bu, John A. Chandy. 235-242 [doi]
• Interleaving Behavioral and Cycle-Accurate Descriptions for Reconfigurable Hardware CompilationJosé Gabriel F. Coutinho, Jun Jiang, Wayne Luk. 245-254 [doi]
• Modeling and FPGA Implementation of Applications Using Parameterized Process Networks with Non-Static ParametersHristo Nikolov, Todor Stefanov, Ed F. Deprettere. 255-263 [doi]
• A BIST Approach for Testing FPGAs Using JBITSM. Y. Niamat, Surya S. Hejeebu, M. Alam. 267-268 [doi]
• Preliminary Report: FPGA Acceleration of Molecular Dynamics ComputationsYongfeng Gu, Tom Van Court, Douglas DiSabello, Martin C. Herbordt. 269-270 [doi]
• A High-Performance Asynchronous FPGA: Test ResultsDavid Fang, John Teifel, Rajit Manohar. 271-272 [doi]
• Considering Run-Time Reconfiguration Overhead in Task Graph Transformations for Dynamically Reconfigurable ArchitecturesSudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt. 273-274 [doi]
• RAVIOLI - Reconfigurable Arithmetic Variable-Precision Implementations of On-Line InstructionsRobert McIlhenny, Milos D. Ercegovac. 275-276 [doi]
• FIFO Communication Models in Operating Systems for Reconfigurable ComputingJohn A. Williams, Neil W. Bergmann, X. Xie. 277-278 [doi]
• Astrophysical Hydrodynamics Simulations on a Reconfigurable SystemNaohito Nakasato, Tsuyoshi Hamada. 279-280 [doi]
• Post Synthesis Level Power Modeling of FPGAsMatthew French, Li Wang, Tyler Anderson, Michael J. Wirthlin. 281-282 [doi]
• FPGA-Based CDMA Switch for Networks-on-ChipDaewook Kim, Manho Kim, Gerald E. Sobelman. 283-284 [doi]
• Design of Networked Reconfigurable Encryption EngineShakith Fernando, Yajun Ha. 285-286 [doi]
• A Virtual Machine for Merit-Based Runtime ReconfigurationBrian Greskamp, Ron Sass. 287-288 [doi]
• Automatic Creation of Domain-Specific Reconfigurable CPLDs for SoCMark Holland, Scott Hauck. 289-290 [doi]
• The GAPLA: A Globally Asynchronous Locally Synchronous FPGA ArchitectureXin Jia, Ranga Vemuri. 291-292 [doi]
• Optimizing Technology Mapping for FPGAs Using CAMsJoshua M. Lucas, Raymond Hoare, Alex K. Jones. 293-294 [doi]
• An Architecture for Video Compression Based on the SCAN AlgorithmH. Sofikitis, K. Roumpou, Apostolos Dollas, Nikolaos G. Bourbakis. 295-296 [doi]
• An Open TCP/IP Core for Reconfigurable LogicApostolos Dollas, Ioannis Ermis, Iosif Koidis, Ioannis Zisis, Christopher Kachris. 297-298 [doi]
• Mutable Codesign for Embedded Protocol ProcessingTodd S. Sproull, Gordon J. Brebner, Christopher E. Neely. 299-300 [doi]
• Accelerating Applications by Mapping Critical Kernels on Coarse-Grain Reconfigurable Hardware in Hybrid SystemsMichalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis. 301-302 [doi]
• An Embedded Reconfigurable Datapath for SoCAndrea Lodi 0002, Luca Ciccarelli, Claudio Mucci, Roberto Giansante, Andrea Cappelli, Mario Toma. 303-304 [doi]
• Systolic Architecture for Computing the Discrete Fourier Transform on FPGAsJ. Greg Nash. 305-306 [doi]
• Hardware Solution to Java Compressed HeapMayumi Kato, Chia-Tien Dan Lo. 307-308 [doi]
• A General Purpose, Highly Efficient Communication Controller Architecture for Hardware Acceleration PlatformsPetersen F. Curt, James P. Durbano, Fernando E. Ortiz, John R. Humphrey, Dennis W. Prather. 309-310 [doi]
• Parallel Hardware Implementation of Cellular Learning Automata Based Evolutionary Computing (CLA-EC) on FPGAArash Hariri, Reza Rastegar, Morteza Saheb Zamani, Mohammad Reza Meybodi. 311-314 [doi]
• Performance and Cost Analysis of Time-Multiplexed Execution on the Dynamically Reconfigurable ProcessorHideharu Amano, Shohei Abe, Yohei Hasegawa, Katsuaki Deguchi, Masayasu Suzuki. 315-316 [doi]
• A System-on-Programmable Chip Approach for MIMO Sphere DecoderJing Ma, Xin-Ming Huang. 317-318 [doi]
• The Erlangen Slot Machine: A Highly Flexible FPGA-Based Reconfigurable PlatformChristophe Bobda, Mateusz Majer, Ali Ahmadinia, Thomas Haller, André Linarth, Jürgen Teich, Sándor P. Fekete, Jan van der Veen. 319-320 [doi]
• Caronte: A Complete Methodology for the Implementation of Partially Dynamically Self-Reconfiguring Systems on FPGA PlatformsAlberto Donato, Fabrizio Ferrandi, Massimo Redaelli, Marco D. Santambrogio, Donatella Sciuto. 321-322 [doi]
• High-Performance FPGA-Based General Reduction MethodsGerald R. Morris, Ling Zhuo, Viktor K. Prasanna. 323-324 [doi]
• Core-Based Methodology: An Automated Approach for Implementing a Complete System from Algorithms to a Heterogeneous Network including FPGAsJasmine Lam, John McAllister, Jennifer Dudley. 325-326 [doi]
• The DARPA Dynamic Programming Benchmark on a Reconfigurable ComputerLuis E. Cordova, Duncan A. Buell, Sreesa Akella. 327-328 [doi]
• Massively Parallel Processors Generator for Reconfigurable SystemTsuyoshi Hamada, Naohito Nakasato. 329-330 [doi]
• FPGA-Based Vector Processing for Solving Sparse Sets of EquationsMuhammad Z. Hasan, Sotirios G. Ziavras. 331-332 [doi]
• Exploiting Multi-Grained Parallelism in Reconfigurable SBC ArchitecturesJoseph Zambreno, Daniel Honbo, Alok N. Choudhary. 333-334 [doi]
• On Distributed Reconfigurable Systems: Open Problems and Some Initial SolutionsApostolos Dollas, Dionissios Efstathiou, Georgios Vernardos, Elias Polytarchos, Konstantinos Kazakos. 335-336 [doi]