Abstract is missing.
- Keynote: Challenges on the Road to Exascale ComputingTilak Agerwala. 1 [doi]
- Keynote: Compilers in the Manycore EraFrançois Bodin. 2-3 [doi]
- Steal-on-Abort: Improving Transactional Memory Performance through Dynamic Transaction ReorderingMohammad Ansari, Mikel Luján, Christos Kotselidis, Kim Jarvis, Chris C. Kirkham, Ian Watson. 4-18 [doi]
- Predictive Runtime Code Scheduling for Heterogeneous ArchitecturesVíctor J. Jiménez, Lluís Vilanova, Isaac Gelado, Marisa Gil, Grigori Fursin, Nacho Navarro. 19-33 [doi]
- Collective OptimizationGrigori Fursin, Olivier Temam. 34-49 [doi]
- High Speed CPU Simulation Using LTU Dynamic Binary TranslationDaniel Jones, Nigel P. Topham. 50-64 [doi]
- Integrated Modulo Scheduling for Clustered VLIW ArchitecturesMattias V. Eriksson, Christoph W. Kessler. 65-79 [doi]
- Software Pipelining in Nested Loops with Prolog-Epilog MergingMohammed Fellahi, Albert Cohen. 80-94 [doi]
- A Flexible Code Compression Scheme Using Partitioned Look-Up TablesMartin Thuresson, Magnus Själander, Per Stenström. 95-109 [doi]
- MLP-Aware Runahead Threads in a Simultaneous Multithreading ProcessorKenzo Van Craeynest, Stijn Eyerman, Lieven Eeckhout. 110-124 [doi]
- IPC Control for Multiple Real-Time Threads on an In-Order SMT ProcessorJörg Mische, Sascha Uhrig, Florian Kluge, Theo Ungerer. 125-139 [doi]
- A Hardware Task Scheduler for Embedded Video ProcessingGhiath Al-Kadi, Andrei Sergeevich Terechko. 140-152 [doi]
- Finding Stress Patterns in Microprocessor WorkloadsFrederik Vandeputte, Lieven Eeckhout. 153-167 [doi]
- Deriving Efficient Data Movement from Decoupled Access/Execute SpecificationsLee W. Howes, Anton Lokhmotov, Alastair F. Donaldson, Paul H. J. Kelly. 168-182 [doi]
- MPSoC Design Using Application-Specific Architecturally Visible CommunicationTheo Kluter, Philip Brisk, Edoardo Charbon, Paolo Ienne. 183-197 [doi]
- Communication Based Proactive Link Power ManagementSai Prashanth Muralidhara, Mahmut T. Kandemir. 198-215 [doi]
- Mapping and Synchronizing Streaming Applications on Cell ProcessorsMaik Nijhuis, Herbert Bos, Henri E. Bal, Cédric Augonnet. 216-230 [doi]
- Adapting Application Mapping to Systematic Within-Die Process Variations on Chip MultiprocessorsYang Ding, Mahmut T. Kandemir, Mary Jane Irwin, Padma Raghavan. 231-247 [doi]
- Accomodating Diversity in CMPs with Heterogeneous FrequenciesMajor Bhadauria, Vincent M. Weaver, Sally A. McKee. 248-262 [doi]
- A Framework for Task Scheduling and Memory Partitioning for Multi-Processor System-on-ChipHassan Salamy, J. Ramanujam. 263-277 [doi]
- Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT ArchitectureMichael B. Henry, Leyla Nazhandali. 278-292 [doi]
- Predictive Thermal Management for Chip Multiprocessors Using Co-designed Virtual MachinesOmer Khan, Sandip Kundu. 293-307 [doi]
- HeDGE: Hybrid Dataflow Graph Execution in the Issue LogicSuriya Subramanian, Kathryn S. McKinley. 308-323 [doi]
- Compiler Controlled Speculation for Power Aware ILP Extraction in Dataflow ArchitecturesMuhammad Umar Farooq, Lizy Kurian John, Margarida F. Jacome. 324-338 [doi]
- Revisiting Cache Block SuperloadingMatthew A. Watkins, Sally A. McKee, Lambert Schaelicke. 339-354 [doi]
- ACM: An Efficient Approach for Managing Shared Caches in Chip MultiprocessorsMohammad Hammoud, Sangyeun Cho, Rami G. Melhem. 355-372 [doi]
- In-Network Caching for Chip MultiprocessorsAditya Yanamandra, Mary Jane Irwin, Vijaykrishnan Narayanan, Mahmut T. Kandemir, Sri Hari Krishna Narayanan. 373-388 [doi]
- Parallel LDPC Decoding on the Cell/B.E. ProcessorGabriel Falcão Paiva Fernandes, Leonel Sousa, Vítor Manuel Mendes da Silva, José Marinho. 389-403 [doi]
- Parallel H.264 Decoding on an Embedded Multicore ProcessorArnaldo Azevedo, Cor Meenderinck, Ben H. H. Juurlink, Andrei Terechko, Jan Hoogerbrugge, Mauricio Alvarez, Alex Ramírez. 404-418 [doi]