Abstract is missing.
- The Optimum Pipeline Depth for a MicroprocessorAllan Hartstein, Thomas R. Puzak. 7-13 [doi]
- The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter DelaysM. S. Hrishikesh, Doug Burger, Stephen W. Keckler, Premkishore Shivakumar, Norman P. Jouppi, Keith I. Farkas. 14-24 [doi]
- Increasing Processor Performance by Implementing Deeper PipelinesEric Sprangle, Doug Carmean. 25 [doi]
- Efficient Dynamic Scheduling Through Tag EliminationDan Ernst, Todd M. Austin. 37-46 [doi]
- Slack: Maximizing Performance Under Technological ConstraintsBrian A. Fields, Rastislav Bodík, Mark D. Hill. 47-58 [doi]
- A Large, Fast Instruction Window for Tolerating Cache MissesAlvin R. Lebeck, Tong Li, Eric Rotenberg, Jinson Koppanalil, Jaidev P. Patwardhan. 59-70 [doi]
- An Instruction Set and Microarchitecture for Instruction Level Distributed ProcessingHo-Seop Kim, James E. Smith. 71 [doi]
- Transient-Fault Recovery Using Simultaneous MultithreadingT. N. Vijaykumar, Irith Pomeranz, Karl Cheng. 87-98 [doi]
- Detailed Design and Evaluation of Redundant Multithreading AlternativesShubhendu S. Mukherjee, Michael Kontz, Steven K. Reinhardt. 99-110 [doi]
- ReVive: Cost-Effective Architectural Support for Rollback Recovery in Shared-Memory MultiprocessorsMilos Prvulovic, Josep Torrellas, Zheng Zhang. 111-122 [doi]
- SafetyNet: Improving the Availability of Shared Memory Multiprocessors with Global Checkpoint/RecoveryDaniel J. Sorin, Milo M. K. Martin, Mark D. Hill, David A. Wood. 123 [doi]
- Dynamic Fine-Grain Leakage Reduction Using Leakage-Biased BitlinesSeongmoo Heo, Kenneth C. Barr, Mark Hampton, Krste Asanovic. 137-147 [doi]
- Drowsy Caches: Simple Techniques for Reducing Leakage PowerKrisztián Flautner, Nam Sung Kim, Steven M. Martin, David Blaauw, Trevor N. Mudge. 148-157 [doi]
- Power and Performance Evaluation of Globally Asynchronous Locally Synchronous ProcessorsAnoop Iyer, Diana Marculescu. 158 [doi]
- Using a User-Level Memory Thread for Correlation PrefetchingYan Solihin, Josep Torrellas, Jaejin Lee. 171-182 [doi]
- Avoiding Initialization Misses to the HeapJarrod A. Lewis, Mikko H. Lipasti, Bryan Black. 183-194 [doi]
- Going the Distance for TLB Prefetching: An Application-Driven StudyGokul B. Kandiraju, Anand Sivasubramaniam. 195 [doi]
- Timekeeping in the Memory System: Predicting and Optimizing Memory BehaviorZhigang Hu, Margaret Martonosi, Stefanos Kaxiras. 209-220 [doi]
- Implementing Optimizations at Decode TimeIlhyun Kim, Mikko H. Lipasti. 221-232 [doi]
- Managing Multi-Configuration Hardware via Dynamic Working Set AnalysisAshutosh S. Dhodapkar, James E. Smith. 233 [doi]
- Queue Pair IP: A Hybrid Architecture for System Area NetworksPhilip Buonadonna, David E. Culler. 247-256 [doi]
- Experiences with VI Communication for Database StorageYuanyuan Zhou, Kai Li, Angelos Bilas, Suresh Jagannathan, Cezary Dubnicki, James Philbin. 257 [doi]
- Speculative Dynamic VectorizationAlex Pajuelo, Antonio González, Mateo Valero. 271-280 [doi]
- Tarantula: A Vector Extension to the Alpha ArchitectureRoger Espasa, Federico Ardanaz, Julio Gago, Roger Gramunt, Isaac Hernandez, Toni Juan, Joel S. Emer, Stephen Felix, P. Geoffrey Lowney, Matthew Mattina, André Seznec. 281 [doi]
- Design Tradeoffs for the Alpha EV8 Conditional Branch PredictorAndré Seznec, Stephen Felix, Venkata Krishnan, Yiannakis Sazeides. 295-306 [doi]
- Difficult-Path Branch Prediction Using Subordinate MicrothreadsRobert S. Chappell, Francis Tseng, Yale N. Patt, Adi Yoaz. 307-317 [doi]
- A Scalable Instruction Queue Design Using Dependence ChainsSteven E. Raasch, Nathan L. Binkert, Steven K. Reinhardt. 318 [doi]