Abstract is missing.
- Ten ways to waste a parallel computerKatherine A. Yelick. 1 [doi]
- Architecting phase change memory as a scalable dram alternativeBenjamin C. Lee, Engin Ipek, Onur Mutlu, Doug Burger. 2-13 [doi]
- A durable and energy efficient main memory using phase change memory technologyPing Zhou, Bo Zhao, Jun Yang, Youtao Zhang. 14-23 [doi]
- Scalable high performance main memory system using phase-change memory technologyMoinuddin K. Qureshi, Vijayalakshmi Srinivasan, Jude A. Rivers. 24-33 [doi]
- Hybrid cache architecture with disparate memory technologiesXiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight, Ramakrishnan Rajamony, Yuan Xie. 34-45 [doi]
- Dynamic MIPS rate stabilization in out-of-order processorsJinho Suh, Michel Dubois. 46-56 [doi]
- Hardware support for WCET analysis of hard real-time multicore systemsMarco Paolieri, Eduardo Quiñones, Francisco J. Cazorla, Guillem Bernat, Mateo Valero. 57-68 [doi]
- Spatio-temporal memory streamingStephen Somogyi, Thomas F. Wenisch, Anastasia Ailamaki, Babak Falsafi. 69-80 [doi]
- Stream chaining: exploiting multiple levels of correlation in data prefetchingPedro Diaz, Marcelo Cintra. 81-92 [doi]
- Architectural core salvaging in a multi-core processor for hard-error toleranceMichael D. Powell, Arijit Biswas, Shantanu Gupta, Shubhendu S. Mukherjee. 93-104 [doi]
- End-to-end register data-flow continuous self-testJavier Carretero, Pedro Chaparro, Xavier Vera, Jaume Abella, Antonio González. 105-115 [doi]
- Memory mapped ECC: low-cost error protection for last level cachesDoe Hyun Yoon, Mattan Erez. 116-127 [doi]
- AnySP: anytime anywhere anyway signal processingMark Woh, Sangwon Seo, Scott A. Mahlke, Trevor N. Mudge, Chaitali Chakrabarti, Krisztián Flautner. 128-139 [doi]
- Rigel: an architecture and scalable programming interface for a 1000-core acceleratorJohn H. Kelm, Daniel R. Johnson, Matthew R. Johnson, Neal C. Crago, William Tuohy, Aqeel Mahesri, Steven S. Lumetta, Matthew I. Frank, Sanjay J. Patel. 140-151 [doi]
- An analytical model for a GPU architecture with memory-level and thread-level parallelism awarenessSunpyo Hong, Hyesoon Kim. 152-163 [doi]
- Multi-execution: multicore caching for data-similar executionsSusmit Biswas, Diana Franklin, Alan Savage, Ryan Dixon, Timothy Sherwood, Frederic T. Chong. 164-173 [doi]
- PIPP: promotion/insertion pseudo-partitioning of multi-core shared cachesYuejian Xie, Gabriel H. Loh. 174-183 [doi]
- Reactive NUCA: near-optimal block placement and replication in distributed cachesNikos Hardavellas, Michael Ferdman, Babak Falsafi, Anastasia Ailamaki. 184-195 [doi]
- A case for bufferless routing in on-chip networksThomas Moscibroda, Onur Mutlu. 196-207 [doi]
- Application-aware deadlock-free oblivious routingMichel A. Kinsy, Myong Hyon Cho, Tina Wen, G. Edward Suh, Marten van Dijk, Srinivas Devadas. 208-219 [doi]
- Indirect adaptive routing on large scale interconnection networksNan Jiang, John Kim, William J. Dally. 220-231 [doi]
- Internet-scale service infrastructure efficiencyJames Hamilton. 232 [doi]
- InvisiFence: performance-transparent memory ordering in conventional multiprocessorsColin Blundell, Milo M. K. Martin, Thomas F. Wenisch. 233-244 [doi]
- Decoupled store completion/silent deterministic replay: enabling scalable data memory for CPR/CFP processorsAndrew D. Hilton, Amir Roth. 245-254 [doi]
- Decoupled DIMM: building high-bandwidth memory system using low-speed DRAM devicesHongzhong Zheng, Jiang Lin, Zhao Zhang, Zhichun Zhu. 255-266 [doi]
- Disaggregated memory for expansion and sharing in blade serversKevin T. Lim, Jichuan Chang, Trevor N. Mudge, Parthasarathy Ranganathan, Steven K. Reinhardt, Thomas F. Wenisch. 267-278 [doi]
- The performance of PC solid-state disks (SSDs) as a function of bandwidth, concurrency, device architecture, and system organizationCagdas Dirik, Bruce Jacob. 279-289 [doi]
- Thread criticality predictors for dynamic performance, power, and resource management in chip multiprocessorsAbhishek Bhattacharjee, Margaret Martonosi. 290-301 [doi]
- Thread motion: fine-grained power management for multi-core systemsKrishna K. Rangan, Gu-Yeon Wei, David Brooks. 302-313 [doi]
- Temperature-constrained power control for chip multiprocessors with online model estimationYefu Wang, Kai Ma, Xiaorui Wang. 314-324 [doi]
- A case for an interleaving constrained shared-memory multi-processorJie Yu, Satish Narayanasamy. 325-336 [doi]
- SigRace: signature-based data race detectionAbdullah Muzahid, Dario Suárez, Shanxiang Qi, Josep Torrellas. 337-348 [doi]
- ECMon: exposing cache events for monitoringVijay Nagarajan, Rajiv Gupta. 349-360 [doi]
- End-to-end performance forecasting: finding bottlenecks before they happenAli G. Saidi, Nathan L. Binkert, Steven K. Reinhardt, Trevor N. Mudge. 361-370 [doi]
- Scaling the bandwidth wall: challenges in and avenues for CMP scalingBrian M. Rogers, Anil Krishna, Gordon B. Bell, Ken V. Vu, Xiaowei Jiang, Yan Solihin. 371-382 [doi]
- A fault tolerant, area efficient architecture for Shor s factoring algorithmMark Whitney, Nemanja Isailovic, Yatish Patel, John Kubiatowicz. 383-394 [doi]
- Performance and power of cache-based reconfigurable computingAndrew Putnam, Susan J. Eggers, Dave Bennett, Eric Dellinger, Jeff Mason, Henry Styles, Prasanna Sundararajan, Ralph Wittig. 395-405 [doi]
- A memory system design framework: creating smart memoriesAmin Firoozshahian, Alex Solomatnikov, Ofer Shacham, Zain Asgar, Stephen Richardson, Christos Kozyrakis, Mark Horowitz. 406-417 [doi]
- Flexible reference-counting-based hardware acceleration for garbage collectionJosé A. Joao, Onur Mutlu, Yale N. Patt. 418-428 [doi]
- Firefly: illuminating future network-on-chip with nanophotonicsYan Pan, Prabhat Kumar, John Kim, Gokhan Memik, Yu Zhang, Alok N. Choudhary. 429-440 [doi]
- Phastlane: a rapid transit optical routing networkMark J. Cianchetti, Joseph C. Kerekes, David H. Albonesi. 441-450 [doi]
- Achieving predictable performance through better memory controller placement in many-core CMPsDennis Abts, Natalie D. Enright Jerger, John Kim, Dan Gibson, Mikko H. Lipasti. 451-461 [doi]
- Dynamic performance tuning for speculative threadsYangchun Luo, Venkatesan Packirisamy, Wei-Chung Hsu, Antonia Zhai, Nikhil Mungre, Ankit Tarkas. 462-473 [doi]
- Boosting single-thread performance in multi-core systems through fine-grain multi-threadingCarlos Madriles, Pedro López, Josep M. Codina, Enric Gibert, Fernando Latorre, Alejandro Martínez, Raúl Martínez, Antonio González. 474-483 [doi]
- Simultaneous speculative threading: a novel pipeline architecture implemented in sun s rock processorShailender Chaudhry, Robert Cypher, Magnus Ekman, Martin Karlsson, Anders Landin, Sherman Yip, Håkan Zeffer, Marc Tremblay. 484-495 [doi]