Abstract is missing.
- A Trimaran Based Framework for Exploring the Design Space of VLIW ASIPs with Coarse Grain Functional UnitsM. Balakrishnan, Anshul Kumar, Paolo Ienne, Anup Gangwar, Bhuvan Middha. 2-7 [doi]
- Tuning of Loop Cache Architectures to Programs in Embedded System DesignFrank Vahid, Susan Cotterell. 8-13 [doi]
- Combined Functional Partitioning and Communication Speed Selection for Networked Voltage-Scalable ProcessorsNader Bagherzadeh, Pai H. Chou, Jinfeng Liu. 14-19 [doi]
- Optimal Message-Passing for Data Coherency in Distributed ArchitectureDaniel Gajski, Junyu Peng. 20-25 [doi]
- Unifying Memory and Processor Wrapper Architecture in Multiprocessor SoC DesignAhmed Amine Jerraya, Damien Lyonnard, Samy Meftali, Frédéric Rousseau, Ferid Gharsalli. 26-31 [doi]
- An Accelerated Datapath Width Optimization Scheme for Area Reduction of Embedded SystemsHiroto Yasuura, Yun Cao, Mohammad Mesbah Uddin. 32-37 [doi]
- Datapath Merging and Interconnection Sharing for Reconfigurable ArchitecturesGuido Araujo, Sharad Malik, Zhining Huang, Nahri Moreano. 38-43 [doi]
- A Run-Time Word-Level Reconfigurable Coarse-Grain Functional Unit for a VLIW ProcessorCarles Rodoreda Sala, Natalino G. Busá. 44-49 [doi]
- Energy/Power Estimation of Regular Processor ArraysSanjay V. Rajopadhye, Steven Derrien. 50-55 [doi]
- Controller Estimation for FPGA Target Architectures during High-Level SynthesisOliver Bringmann, Wolfgang Rosenstiel, Carsten Menn. 56-61 [doi]
- System-Level Modeling of a Network Switch SoCAndrew S. Cassidy, Christopher P. Andrews, Donald E. Thomas, JoAnn M. Paul. 62-67 [doi]
- Multiprocessor Mapping of Process Networks: A JPEG Decoding Case StudyErwin A. de Kock. 68-73 [doi]
- System-Level Design of IEEE1394 Bus Segment BridgeTakao Onoye, Yukihiro Nakamura, Atsuhito Shigiya, Keishi Chikamura, Kosuke Tsujino, Tomonori Izumi, Hirofumi Yamamoto. 74-79 [doi]
- Security-Driven Exploration of Cryptography in DSP CoresCatherine H. Gebotys. 80-85 [doi]
- A Case Study of Hardware and Software Synthesis in ForSyDeIngo Sander, Axel Jantsch, Zhonghai Lu. 86-91 [doi]
- An Adaptive Low-Power Transmission Scheme for On-Chip NetworksPaolo Ienne, Patrick Thiran, Giovanni De Micheli, Frederic Worm. 92-100 [doi]
- CMP on SoC: Architect s ViewShuichi Sakai. 101-102 [doi]
- Design Experience of a Chip Multiprocessor Merlot and Expectation to Functional VerificationSatoshi Matsushita. 103-108 [doi]
- OpenMP: Parallel Programming API for Shared Memory Multiprocessors and On-Chip MultiprocessorsMitsuhisa Sato. 109-111 [doi]
- Managing Dynamic Concurrent Tasks in Embedded Real-Time Multimedia SystemsRudy Lauwereins, Chun Wong, Paul Marchal, Johan Vounckx, Patrick David, Stefaan Himpe, Francky Catthoor, Peng Yang. 112-119 [doi]
- A Design Space Exploration Framework for Reduced Bit-Width Instruction Set Architecture (rISA) Design Alexandru Nicolau, Nikil D. Dutt, Aviral Shrivastava, Partha Biswas, Ashok Halambi. 120-125 [doi]
- Timing Analysis of Embedded Software for Speculative ProcessorsAbhik Roychoudhury, Xianfeng Li, Tulika Mitra. 126-131 [doi]
- Modeling Assembly Instruction Timing in Superscalar ArchitecturesWilliam Fornaciari, Vito Trianni, Carlo Brandolese, Donatella Sciuto, Fabio Salice, Giovanni Beltrame. 132-137 [doi]
- Code Compression for VLIW Processors Using Variable-to-Fixed CodingHaris Lekatsas, Wayne Wolf, Yuan Xie. 138-143 [doi]
- Optimal Code Size Reduction for Software-Pipelined and Unfolded LoopsBin Xiao, Zili Shao, Chantana Chantrapornchai, Edwin Hsing-Mean Sha, Qingfeng Zhuge. 144-149 [doi]
- The Formal Execution Semantics of SpecCRainer Dömer, Andreas Gerstlauer, Wolfgang Müller 0003. 150-155 [doi]
- Formal Verification in a Component-Based Reuse MethodologyPetru Eles, Zebo Peng, Daniel Karlsson. 156-161 [doi]
- Validation in a Component-Based Design Flow for Multicore SoCsAhmed Amine Jerraya, Sungjoo Yoo, Aimen Bouchhima, Gabriela Nicolescu. 162-167 [doi]
- Efficient Simulation of Synthesis-Oriented System Level DesignsRajesh K. Gupta, Sandeep K. Shukla, Nick Savoiu. 168-173 [doi]
- Virtual Synchronization for Fast Distributed Cosimulation of Dataflow Task GraphsSoonhoi Ha, Sungchan Kim, Chan-Eun Rhee, Hyunguk Jung, Youngmin Yi, Dohyung Kim. 174-179 [doi]
- A New Performance Evaluation Approach for System Level Design Space ExplorationM. Balakrishnan, Anshul Kumar, C. P. Joshi. 180-185 [doi]
- A Visual Approach to Validating System Level DesignsJürgen Ruf, Thomas Kropf, Jochen Klose. 186-191 [doi]
- Special Session: Security on SoCHiroto Yasuura, Naofumi Takagi, Srivaths Ravi, Michael Torla, Catherine H. Gebotys. 192-194 [doi]
- Securing Wireless Data: System Architecture ChallengesAnand Raghunathan, Nachiketh R. Potlapally, Srivaths Ravi. 195-200 [doi]
- Data Memory Design Considering Effective Bitwidth for Low-Energy Embedded SystemsHiroto Yasuura, Hiroyuki Tomiyama, Takanori Okuma, Yun Cao. 201-206 [doi]
- Efficient Power Reduction Techniques for Time Multiplexed Address BusesNikil D. Dutt, Daniel S. Hirschberg, Mahesh Mamidipaka. 207-212 [doi]
- Reducing Energy Consumption by Dynamic Copying of Instructions onto Onchip MemoryM. Balakrishnan, Peter Marwedel, Lars Wehmeyer, Nils Grunwald, Rajeshwari Banakar, Stefan Steinke. 213-218 [doi]
- Low-Power Data Memory Communication for Application-Specific Embedded ProcessorsAlex Orailoglu, Peter Petrov. 219-224 [doi]
- System Level Power-Performance Trade-Offs in Embedded Systems Using Voltage and Frequency Scaling of Off-Chip Buses and MemoryAbhijit Chatterjee, Peeter Ellervee, Vincent John Mooney III, Jun-Cheol Park, Kyu-won Choi, Kiran Puttaswamy. 225-230 [doi]
- System-Level Abstraction SemanticsDaniel Gajski, Andreas Gerstlauer. 231-236 [doi]
- A Symbolic Approach for the Combined Solution of Scheduling and AllocationLuciano Lavagno, Mihai T. Lazarescu, Stefano Quer, Sergio Nocco, Claudio Passerone, Gianpiero Cabodi. 237-242 [doi]
- Round-Robin Arbiter Design and GenerationVincent John Mooney III, George F. Riley, Eung S. Shin. 243-248 [doi]
- An Object-Oriented Design Process for System-on-Chip Using UMLTsuneo Nakata, Akio Matsuda, Minoru Shoji, Shinya Kuwamura, Qiang Zhu. 249-254 [doi]
- Improving Embedded System Design by Means of HW-SW Compilation on Reconfigurable CoprocessorsJuan Carlos López, Fernando Rincón, Francisco Moya, José Manuel Moya. 255-260 [doi]
- Dynamic Common Sub-Expression Elimination during Scheduling in High-Level SynthesisAlexandru Nicolau, Nikil D. Dutt, Rajesh Gupta, Nick Savoiu, Mehrdad Reshadi, Sumit Gupta. 261-266 [doi]