Abstract is missing.
- Modeling and Evaluating Carbon Nanotube Bundles for Future VLSI Interconnect ApplicationsYehia Massoud, Arthur Nieuwoudt. 1-5 [doi]
- Routing Aware Switch Hardware Customization for Networks on ChipsPaolo Meloni, Srinivasan Murali, Salvatore Carta, Massimo Camplani, L. Raffo, Giovanni De Micheli. 1-5 [doi]
- Novel Design of Three-Dimensional Crossbar for Future Network on Chip based on Post-Silicon DevicesKumiko Nomura, Keiko Abe, Shinobu Fujita, André DeHon. 1-5 [doi]
- Hybrid Nanostructures: Organic Interconnections and Device ApplicationsSandro Carrara, Bruno Samorì, Sigrid Bernstorff, Maria Di Pasquale, Alberto Ansaldo, Maria Teresa Parodi, Davide Ricci, Ermanno Di Zitti. 1-5 [doi]
- Nanoscale Data Storage Devices Capacity and Encoding SchemesPaul P. Sotiriadis. 1-4 [doi]
- Self-Assembled Networks: Control vs. ComplexityJaidev P. Patwardhan, Chris Dwyer, Alvin R. Lebeck. 1-5 [doi]
- Can Carbon Nanotubes Extend the Lifetime of On-Chip Electrical Interconnections?Kaustav Banerjee, Sungjun Im, Navin Srivastava. 1-9 [doi]
- Predictive Technology Model for Nano-CMOS Design ExplorationYu Cao, Wei Zhao. 1-5 [doi]
- Optimizing Dielectric Strip Plasmonic Waveguides for Subwavelength On-Chip Optical CommunicationAmir Hosseini, Arthur Nieuwoudt, Yehia Massoud. 1-5 [doi]
- Electron Beam-induced Light Emission and Transport in GaN NanowiresJoseph Tringe, Warren MoberlyChan, Charles Stevens, Albert Davydov, Abhishek Motayed. 1-4 [doi]
- Controlled nanowire fabrication by PEDAL processSachin Sonkusale, Paul D. Franzon. 1-8 [doi]
- On-Chip Interconnects and Repeaters Based on NiSi NanowiresWei Wang 0003, Adam Maina Ari, Woon Ket Wong. 1-5 [doi]
- Connecting and Configuring Defective Nano-Scale Networks for DNA Self-AssemblyLuke Demoracski, Fabrizio Lombardi. 1-5 [doi]
- Future Trends on Nanoantennas SynthesisDavide Franceschini, Massimo Donelli, Renzo Azaro, Andrea Massa. 1-5 [doi]
- A Theoretical Framework for On-chip Stochastic Communication AnalysisPaul Bogdan, Radu Marculescu. 1-5 [doi]
- The State of ZettaRAMEric Rotenberg, Ravi V. Venkatesan. 1-5 [doi]
- Skew Insensitive Physical Links for Network on ChipDaniele Mangano, Riccardo Locatelli, Alberto Scandurra, Carlo Pistritto, Marcello Coppola, Luca Fanucci, Francesco Vitullo, Dario Zandri. 1-5 [doi]
- Reliability Analysis for On-chip Networks under RC Interconnect Delay VariationMosin Mondal, Xiang Wu, Adnan Aziz, Yehia Massoud. 1-5 [doi]
- 3D Nanowire-Based Programmable LogicBenjamin Gojman, Raphael Rubin, Concetta Pilotto, André DeHon, Tetsufumi Tanamoto. 1-5 [doi]
- Design and Simulation of Logic Circuits with Hybrid Architectures of Single Electron Transistors and Conventional DevicesAranggan Venkataratnam, Ashok K. Goel. 1-5 [doi]
- Graph Spectra of Carbon Nanotube NetworksStephen F. Bush, Sanjay Goel. 1-10 [doi]
- A Distributed Multi-Point Network Interface for Low-Latency, Deadlock-Free On-Chip InterconnectsDongkook Park, Chrysostomos Nicopoulos, Jongman Kim, Narayanan Vijaykrishnan, Chita R. Das. 1-6 [doi]
- Area and Power Modeling Methodologies for Networks-on-ChipPaolo Meloni, Salvatore Carta, Roberto Argiolas, Luigi Raffo, Federico Angiolini. 1-7 [doi]
- Multipolar Photonic Interactions for Interconnections and Logical Operations in Nanostructure NetworksHideaki Matsueda. 1-5 [doi]
- Optical Interconnects for Network on ChipAlberto Scandurra, Maurizio Lenzi, Ranieri Guerra, Francesco G. Della Corte, Maria Arcangela Nigro. 1-5 [doi]
- A Low Cost Network-on-Chip with Guaranteed Service Well Suited to the GALS ApproachIvan Miro Panades, Alain Greiner, Abbas Sheibanyrad. 1-5 [doi]
- On Information Transmission Among NanomachinesGiuseppa Alfano, Daniele Miorandi. 1-5 [doi]
- 3D on-chip networking technology based on post-silicon devices for future networks-on-chipShinobu Fujita, Kumiko Nomura, Keiko Abe, Thomas H. Lee. 1-5 [doi]