Abstract is missing.
- System-Level Design Methods for Low-Energy Architectures Containing Variable Voltage ProcessorsFlavius Gruian. 1-12 [doi]
- Ramp Up/Down Functional Unit to Reduce Step PowerZhenyu Tang, Norman Chang, Shen Lin, Weize Xie, O. Sam Nakagawa, Lei He. 13-24 [doi]
- An Adaptive Issue Queue for Reduced Power at High PerformanceAlper Buyuktosunoglu, Stanley Schuster, David Brooks, Pradip Bose, Peter W. Cook, David H. Albonesi. 25-39 [doi]
- Dynamic Memory Oriented Transformations in the MPEG4 IM1-Player on a Low Power PlatformPaul Marchal, Chun Wong, Aggeliki S. Prayati, Nathalie Cossement, Francky Catthoor, Rudy Lauwereins, Diederik Verkest, Hugo De Man. 40-50 [doi]
- Exploiting Content Variation and Perception in Power-Aware 3D Graphics RenderingJeongseon Euh, Wayne Burleson. 51-64 [doi]
- Compiler-Directed Dynamic Frequency and Voltage SchedulingChung-Hsing Hsu, Ulrich Kremer, Michael S. Hsiao. 65-81 [doi]
- Cache-Line Decay: A Mechanism to Reduce Cache Leakage PowerStefanos Kaxiras, Zhigang Hu, Girija J. Narlikar, Rae McLellan. 82-96 [doi]
- Dynamically Reconfiguring Processor Resources to Reduce Power Consumption in High-Performance ProcessorsRoberto Maro, Yu Bai, R. Iris Bahar. 97-111 [doi]
- TEM:::2:::P:::2:::EST: A Thermal Enabled Multi-model Power/Performance ESTimatorAshutosh S. Dhodapkar, Chee How Lim, George Cai, W. Robert Daasch. 112-125 [doi]
- Power-Performance Modeling and Tradeoff Analysis for a High End MicroprocessorDavid Brooks, Margaret Martonosi, John-David Wellman, Pradip Bose. 126-136 [doi]
- A Comparison of Two Architectural Power ModelsSoraya Ghiasi, Dirk Grunwald. 137-152 [doi]