Abstract is missing.
- Platform Thinking in Embedded SystemsRobert A. Iannucci. 1 [doi]
- Interprocedural Optimization for Dynamic Hardware ConfigurationsElena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis. 2-11 [doi]
- Reconfigurable Embedded Systems: An Application-Oriented Perspective on Architectures and Design TechniquesManfred Glesner, Heiko Hinkelmann, Thomas Hollstein, Leandro Soares Indrusiak, Tudor Murgan, Abdulfattah Mohammad Obeid, Mihail Petrov, Thilo Pionteck, Peter Zipf. 12-21 [doi]
- Reconfigurable Multiple Operation ArrayHumberto Calderon, Stamatis Vassiliadis. 22-31 [doi]
- RAPANUI: Rapid Prototyping for Media Processor Architecture ExplorationGuillermo Payá Vayá, Javier Martín-Langerwerf, Peter Pirsch. 32-40 [doi]
- Data-Driven Regular Reconfigurable Arrays: Design Space Exploration and MappingRicardo Ferreira, João M. P. Cardoso, Andre Toledo, Horácio C. Neto. 41-50 [doi]
- Automatic FIR Filter Generation for FPGAsHolger Ruckdeschel, Hritam Dutta, Frank Hannig, Jürgen Teich. 51-61 [doi]
- Two-Dimensional Fast Cosine Transform for Vector-STA ArchitecturesPablo Robelly, A. Lehmann, Gerhard Fettweis. 62-71 [doi]
- Configurable Computing for High-Security/High-Performance Ambient SystemsGuy Gogniat, Wayne Burleson, Lilian Bossuet. 72-81 [doi]
- FPL-3E: Towards Language Support for Reconfigurable Packet ProcessingMihai-Lucian Cristea, Claudiu Zissulescu, Ed F. Deprettere, Herbert Bos. 82-92 [doi]
- Flux Caches: What Are They and Are They Useful?Georgi Gaydadjiev, Stamatis Vassiliadis. 93-102 [doi]
- First-Level Instruction Cache Design for Reducing Dynamic Energy ConsumptionCheol Hong Kim, Sung-Hoon Shim, Jong Wook Kwak, Sung Woo Chung, Chu Shik Jhon. 103-111 [doi]
- A Novel JAVA Processor for Embedded DevicesYiyu Tan, Chihang Yau, Kaiman Lo, Pak Lun Mok, Anthony S. Fong. 112-121 [doi]
- Formal Specification of a Protocol ProcessorTomi Westerlund, Juha Plosila. 122-131 [doi]
- Tuning a Protocol Processor Architecture Towards DSP OperationsJani Paakkulainen, Seppo Virtanen, Jouni Isoaho. 132-141 [doi]
- Observations on Power-Efficiency Trends in Mobile Communication DevicesOlli Silvén, Kari Jyrkkä. 142-151 [doi]
- CORDIC-Augmented Sandbridge Processor for Channel EqualizationMihai Sima, John Glossner, Daniel Iancu, Hua Ye, Andrei Iancu, A. Joseph Hoane. 152-161 [doi]
- Power-Aware Branch Logic: A Hardware Based Technique for Filtering Access to Branch LogicSung-Hoon Shim, Jong Wook Kwak, Cheol Hong Kim, Sung Tae Jhang, Chu Shik Jhon. 162-171 [doi]
- Exploiting Intra-function Correlation with the Global History StackFei Gao, Suleyman Sair. 172-181 [doi]
- Power Efficient Instruction Caches for Embedded SystemsDinesh C. Suresh, Walid A. Najjar, Jun Yang. 182-191 [doi]
- Micro-architecture Performance Estimation by FormulaLucanus J. Simonson, Lei He. 192-201 [doi]
- Offline Phase Analysis and Optimization for Multi-configuration ProcessorsFrederik Vandeputte, Lieven Eeckhout, Koen De Bosschere. 202-211 [doi]
- Hardware Cost Estimation for Application-Specific Processor DesignTeemu Pitkänen, Tommi Rantanen, Andrea G. M. Cilio, Jarmo Takala. 212-221 [doi]
- Ultra Fast Cycle-Accurate Compiled Emulation of Inorder Pipelined ArchitecturesStefan Farfeleder, Andreas Krall, R. Nigel Horspool. 222-231 [doi]
- Generating Stream Based Code from Plain CMarcel Beemster, Hans van Someren, Liam Fitzpatrick, Ruben van Royen. 232-241 [doi]
- Fast Real-Time Job Selection with Resource Constraints Under Earliest Deadline FirstSangchul Han, Moonju Park, Yookun Cho. 242-250 [doi]
- A Programming Model for an Embedded Media Processing ArchitectureDan Zhang, Zeng-zhi Li, Hong Song, Long Liu. 251-261 [doi]
- Automatic ADL-Based Assembler Generation for ASIP Programming SupportLeonardo Taglietti, José O. Carlomagno Filho, Daniel C. Casarotto, Olinto J. V. Furtado, Luiz C. V. dos Santos. 262-268 [doi]
- Sandbridge Software ToolsC. John Glossner, Sean Dorward, Sanjay Jinturkar, Mayan Moudgill, Erdem Hokenek, Michael J. Schulte, Stamatis Vassiliadis. 269-278 [doi]
- A Hardware Accelerator for Controlling Access to Multiple-Unit Resources in Safety/Time-Critical SystemsPhilippe Marchand, Purnendu Sinha. 279-288 [doi]
- Pattern Matching Acceleration for Network Intrusion Detection SystemsSunil Kim. 289-298 [doi]
- Real-Time Stereo Vision on a Reconfigurable SystemSunghwan Lee, JongSu Yi, JunSeong Kim. 299-307 [doi]
- Application of Very Fast Simulated Reannealing (VFSR) to Low Power DesignAli Manzak, Hüseyin Göksu. 308-313 [doi]
- Compressed Swapping for NAND Flash Memory Based Embedded SystemsSangduck Park, Hyunjin Lim, Hoseok Chang, Wonyong Sung. 314-323 [doi]
- A Radix-8 Multiplier Design and Its Extension for Efficient Implementation of Imaging AlgorithmsDavid Guevorkian, Petri Liuha, Aki Launiainen, Konsta Punkka, Ville Lappalainen. 324-333 [doi]
- A Scalable Embedded JPEG2000 ArchitectureChunhui Zhang, Yun Long, Fadi J. Kurdahi. 334-343 [doi]
- A Routing Paradigm with Novel Resources Estimation and Routability Models for X-Architecture Based Physical DesignYu Hu, Tong Jing, Xianlong Hong, Xiaodong Hu, Guiying Yan. 344-353 [doi]
- Benchmarking Mesh and Hierarchical Bus Networks in System-on-Chip ContextErno Salminen, Tero Kangas, Jouni Riihimäki, Vesa Lahtinen, Kimmo Kuusilinna, Timo D. Hämäläinen. 354-363 [doi]
- DDM-CMP: Data-Driven Multithreading on a Chip MultiprocessorKyriakos Stavrou, Paraskevas Evripidou, Pedro Trancoso. 364-373 [doi]
- Modeling NoC Architectures by Means of Deterministic and Stochastic Petri NetsHolger Blume, Thorsten von Sydow, Daniel Becker, Tobias G. Noll. 374-383 [doi]
- High Abstraction Level Design and Implementation Framework for Wireless Sensor NetworksMauri Kuorilehto, Mikko Kohvakka, Marko Hännikäinen, Timo D. Hämäläinen. 384-393 [doi]
- The ODYSSEY Tool-Set for System-Level Synthesis of Object-Oriented ModelsMaziar Goudarzi, Shaahin Hessabi. 394-403 [doi]
- Design and Implementation of a WLAN Terminal Using UML 2.0 Based Design FlowPetri Kukkala, Marko Hännikäinen, Timo D. Hämäläinen. 404-413 [doi]
- Rapid Implementation and Optimisation of DSP Systems on SoPC Heterogeneous PlatformsJohn McAllister, Roger Woods, D. Reilly, Scott Fischaber, R. Hasson. 414-423 [doi]
- DVB-DSNG Modem High Level Synthesis in an Optimized Latency Insensitive System ContextPierre Bomel, Nabil Abdelli, Eric Martin, Anne-Marie Fouilliart, Emmanuel Boutillon, Philippe Kajfasz. 424-433 [doi]
- SystemQ: A Queuing-Based Approach to Architecture Performance Evaluation with SystemCSören Sonntag, Matthias Gries, Christian Sauer. 434-444 [doi]
- Moving Up to the Modeling Level for the Transformation of Data Structures in Embedded Multimedia ApplicationsMarijn Temmerman, Edgar G. Daylight, Francky Catthoor, Serge Demeyer, Tom Dhaene. 445-454 [doi]
- A Case for Visualization-Integrated System-Level Design Space ExplorationAndy D. Pimentel. 455-464 [doi]
- s Mixed Virtual/Real Prototypes for Incremental System Design - A Proof of ConceptStefan Eilers, Christian Müller-Schloer. 465-474 [doi]