Abstract is missing.
- Multi-level Parallelism in the Computational Modeling of the HeartCarolina Ribeiro Xavier, Rafael Sachetto Oliveira, Vinicius Vieira, Rodrigo Weber dos Santos, Wagner Meira Jr.. 3-10 [doi]
- Computational Characteristics of Production Seismic Migration and its Performance on Novel Processor ArchitecturesJairo Panetta, Paulo R. P. de Souza Filho, Carlos A. da Cunha Filho, Fernando M. Roxo da Motta, Silvio Sinedino Pinheiro, Ivan Pedrosa Junior, Andre L. Romanelli Rosa, Luiz R. Monnerat, Leandro T. Carneiro, Carlos H. B. de Albrecht. 11-18 [doi]
- Voice Command Recognition with Dynamic Time Warping (DTW) using Graphics Processing Units (GPU) with Compute Unified Device Architecture (CUDA)Gustavo Poli, João F. Mari, José Hiroki Saito, Alexandre L. M. Levada. 19-25 [doi]
- Exploring Novel Parallelization Technologies for 3-D Imaging ApplicationsDiego Rivera, Dana Schaa, Micha Moffie, David R. Kaeli. 26-33 [doi]
- Low-cost Techniques for Reducing Branch Context Pollution in a Soft Realtime Embedded Multithreaded ProcessorEmre Özer, Alastair Reid, Stuart Biles. 37-44 [doi]
- Self-Imposed Temporal Redundancy: An Efficient Technique to Enhance the Reliability of Pipelined Functional UnitsElias Mizan, Tileli Amimeur, Margarida F. Jacome. 45-53 [doi]
- Predicting Loop Termination to Boost Speculative Thread-Level Parallelism in Embedded ApplicationsMd. Mafijul Islam. 54-61 [doi]
- Multi2Sim: A Simulation Framework to Evaluate Multicore-Multithreaded ProcessorsRafael Ubal, Julio Sahuquillo, Salvador Petit, Pedro López. 62-68 [doi]
- Performance Improvement of the Parallel Lattice Boltzmann Method Through Blocked Data DistributionsClaudio Schepke, Nicolas Maillard. 71-78 [doi]
- A Scalable Parallel Deduplication AlgorithmWalter Santos, Thiago Teixeira, Carla Machado, Wagner Meira Jr., Renato Ferreira, Dorgival Olavo Guedes Neto, Altigran Soares da Silva. 79-86 [doi]
- A Multigrid-Schwarz Method for the Solution of Hydrodynamics and Heat Transfer Problems in Unstructured MeshesGuilherme Galante, Rogério Luis Rizzi, Tiarajú Asmuz Diverio. 87-94 [doi]
- Performance Evaluation of the Dual-Core Based SGI Altix 4700Rod Fatoohi. 97-104 [doi]
- Impacts of Multiprocessor Configurations on Workloads in BioinformaticsYoufeng Wu, Mauricio Breternitz Jr., Victor Ying. 105-113 [doi]
- Efficient Hardware for Modular Exponentiation Using the Sliding-Window Method with Variable-Length PartitioningNadia Nedjah, Luiza de Macedo Mourelle. 117-124 [doi]
- Optimized Math Functions for a Fixed-Point DSP ArchitectureKarlo Gusso Lenzi, Osamu Saotome. 125-132 [doi]
- A Component-Oriented Support for Hierarchical MPI Programming on Multi-Cluster Grid EnvironmentsElton N. Mathias, Françoise Baude, Vincent Cave, Nicolas Maillard. 135-142 [doi]
- A Selector of Grid Resources based on the Semantic Integration of Multiple OntologiesAlexandre P. C. Silva, Mario A. R. Dantas. 143-150 [doi]
- A Novel Algorithm for Indirect Reputation-Based Grid Resource ManagementJavier Echaiz, Jorge Ardenghi, Guillermo Ricardo Simari. 151-158 [doi]
- Register File Energy Optimization for Snooping Based Clustered VLIW ArchitecturesRahul Nagpal, Y. N. Srikant. 161-168 [doi]
- Queue Register File Optimization Algorithm for QueueCore ProcessorArquimedes Canedo, Ben A. Abderazek, Masahiro Sowa. 169-176 [doi]
- An Intelligent Mechanism to Explore a Two-Level Cache Hierarchy Considering Energy Consumption and Time PerformanceAbel G. Silva-Filho, Carmelo J. A. Bastos Filho, Ricardo Massa Ferreira Lima, Davi M. A. Falcão, Filipe R. Cordeiro, Marília P. Lima. 177-184 [doi]
- A Code Compression Method to Cope with Security Hardware OverheadsEduardo Wanderley Netto, Romain Vaslin, Guy Gogniat, Jean-Philippe Diguet. 185-192 [doi]
- Architectural Breakdown of End-to-End Latency in a TCP/IP NetworkSteen Larsen, Parthasarathy Sarangam, Ram Huggahalli. 195-202 [doi]
- Performance Analysis and Linear Optimization Modeling of All-to-all Collective Communication AlgorithmsHyacinthe Nzigou Mamadou, Takeshi Nanri, Kazuaki Murakami, Guilherme de Melo Baptista Domingues. 203-210 [doi]
- Design of a Feasible On-Chip Interconnection Network for a Chip Multiprocessor (CMP)Seung Eun Lee, Jun Ho Bahn, Nader Bagherzadeh. 211-218 [doi]
- Node Level Primitives for Parallel Exact InferenceYinglong Xia, Viktor K. Prasanna. 221-228 [doi]
- Fault-tolerance in filter-labeled-stream applicationsBruno Coutinho, Dorgival Olavo Guedes Neto, Wagner Meira Jr., Renato Ferreira. 229-236 [doi]
- High-Level Service Connectors for Component-Based High Performance ComputingFrancisco Heron de Carvalho Junior, Ricardo Cordeiro Corrêa, Gisele Azevedo Araújo, Jefferson Carvalho Silva, Rafael Dueire Lins. 237-244 [doi]
- On-line Scheduling of MPI-2 Programs with Hierarchical Work StealingGuilherme P. Pezzi, Márcia C. Cera, Elton N. Mathias, Nicolas Maillard, Philippe Olivier Alexandre Navaux. 247-254 [doi]
- Exigency-based real-time scheduling policy to provide absolute QoS for web servicesLucas S. Casagrande, Rodrigo Fernandes de Mello, Ricardo Bertagna, Jose Augusto Andrade Filho, Francisco José Monaco. 255-262 [doi]
- DTA-C: A Decoupled multi-Threaded Architecture for CMP SystemsRoberto Giorgi, Zdravko Popovic, Nikola Puzovic. 263-270 [doi]
- Automatic Constraint Partitioning to Speed Up CLP ExecutionMarluce Rodrigues Pereira, Patrícia Kayser Vargas, Maria Clicia Stelling de Castro, Felipe Maia Galvão França, Inês de Castro Dutra. 271-278 [doi]