Masahiro Sowa - researchr alias

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Viewing Publication 1 - 39 from 39

2012

An FPGA-Based Information Detection Hardware System Employing Multi-Match Content Addressable MemoryDuc-Hung Le, Katsumi Inoue, Masahiro Sowa, Cong-Kha Pham. ieicet, 95-A(10):1708-1717, 2012. [doi]

2010

Compiling for Reduced Bit-Width Queue ProcessorsArquimedes Canedo, Ben A. Abderazek, Masahiro Sowa. vlsisp, 59(1):45-55, 2010. [doi]

2009

Efficient compilation for queue size constrained queue processorsArquimedes Canedo, Ben A. Abderazek, Masahiro Sowa. pc, 35(4):213-225, 2009. [doi]

Compiler Support for Code Size Reduction Using a Queue-Based ProcessorArquimedes Canedo, Ben A. Abderazek, Masahiro Sowa. thipeac, 2:269-285, 2009. [doi]

Design and implementation of a queue compilerArquimedes Canedo, Ben A. Abderazek, Masahiro Sowa. mam, 33(2):129-138, 2009. [doi]

2008

2007

Mathematical Model for Multiobjective Synthesis of NoC ArchitecturesBen A. Abderazek, Mushfiquzzaman Akanda, Tsutomu Yoshinaga, Masahiro Sowa. icppw 2007: 36 [doi]

Dual-Execution Mode Processor Architecture For Embedded ApplicationsMd. Musfiquzzaman Akanda, Ben A. Abderazek, Masahiro Sowa. jmm, 3(4):347-370, 2007. [doi]

An Efficient Code Generation Algorithm for Code Size Reduction Using 1-Offset P-Code Queue Computation ModelArquimedes Canedo, Ben A. Abderazek, Masahiro Sowa. euc 2007: 196-208 [doi]

Queue Register File Optimization Algorithm for QueueCore ProcessorArquimedes Canedo, Ben A. Abderazek, Masahiro Sowa. sbac-pad 2007: 169-176 [doi]

New Code Generation Algorithm for QueueCoreAn Embedded Processor with High ILPArquimedes Canedo, Ben A. Abderazek, Masahiro Sowa. pdcat 2007: 185-192 [doi]

Optimizing Reaching Definitions Overhead in Queue ProcessorsYuki Nakanishi, Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa. jcit, 2(4):36-40, 2007. [doi]

2006

2005

2003

On the Design of a Register Queue Based Processor Architecture (FaRM-rq)Ben A. Abderazek, Soichi Shigeta, Tsutomu Yoshinaga, Masahiro Sowa. ispa 2003: 248-262 [doi]

2002

Compiler-Controlled Parallelism-Independent Scheduling Method for Cluster Computing SystemsKirilka Nikolova, Masahiro Sowa. hpcs 2002: 182-189 [doi]

Compiler-Controlled Parallelism-Independent Scheduling for Parallel and Distributed SystemsKirilka Nikolova, Sou Pei You, Masahiro Sowa. para 2002: 484-493 [doi]

Proposal and Design of a Parallel Queue Processor Architecture (PQP)Masahiro Sowa, Ben A. Abderazek, Soichi Shigeta, Kirilka Nikolova, Tsutomu Yoshinaga. pdcs 2002: 549-554

2001

Access route control by an extended key/lock schemeSoichi Shigeta, Kentaro Shimizu, Masahiro Sowa. csse, 16(5):319-325, 2001.

1997

Program Controlled Cache Memory on Parallel ComputerMitsuaki Nakasumi, Shusuke Okamoto, Masahiro Sowa. pdpta 1997: 1423-1433

Intruction Fetch Mechanism for PN-SuperscalarShusuke Okamoto, Masahiro Sowa. pdpta 1997: 1406-1410

1996

Hybrid Processor Based on VLIW and PN-SuperscalarShusuke Okamoto, Masahiro Sowa. pdpta 1996: 623-632

1994

V++: An Instruction-Restructurable Processor ArchitectureTakaya Arita, Hiromitsu Takagi, Masahiro Sowa. hicss 1994: 398-408

1993

A static processor-scheduling algorithm resistive to dynamic fluctuation of execution timingHiromitsu Takagi, Takaya Arita, Masahiro Sowa. scjapan, 24(8):1-10, 1993. [doi]

1992

Performance of the PN superscalar processor as estimated by simulationTakaya Arita, Hiroaki Ito, Masahiro Sowa. scjapan, 23(14):24-34, 1992. [doi]

Delayed instruction execution on a long instruction word (LIW) computerKomei Kato, Takaya Arita, Masahiro Sowa. scjapan, 23(14):13-23, 1992. [doi]

1991

High Speed Synchronization for a Statically Scheduled Superscalar ProcessorTakaya Arita, Masahiro Sowa. ijhsc, 3(1):77-87, 1991. [doi]

Parallel execution on the function-partitioned processor with multiple instruction streamsMasahiro Sowa, Takaya Arita, Tadaaki Kawamura, Hiromitsu Takagi. scjapan, 22(4):22-28, 1991. [doi]

1987

Performance of a simulated dataflow computer DFNDR-2Masahiro Sowa, Akitoshi Kamimura. scjapan, 18(6):100-113, 1987. [doi]

1985

A Timed Petri Net Model and Simulation of a Dataflow ComputerT. Smigelski, Tadao Murata, Masahiro Sowa. pnpm 1985: 56-63

1982

A Data Flow Computer Architecture with Program and Token MemoriesMasahiro Sowa, Tadao Murata. TC, 31(9):820-824, 1982.

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