Table of Contents

• A highly parallel Turbo Product Code decoder without interleaving resourceCamille Leroux, Christophe Jégo, Patrick Adde, Michel Jézéquel, Deepak Gupta. 1-6 [doi]
• A digit-serial architecture for inversion and multiplication in GF(2:::M:::)Junfeng Fan, Ingrid Verbauwhede. 7-12 [doi]
• Unified decoder architecture for LDPC/turbo codesYang Sun, Joseph R. Cavallaro. 13-18 [doi]
• Efficient interpolration architecture for soft-decision Reed-Solomon decoding by applying slow-downXinmiao Zhang, Jiangli Zhu. 19-24 [doi]
• A 100MHz real-time tone mapping processor with integrated photographic and gradient compression in 0.13 mum technologyChing-Te Chiu, Tsun-Hsien Wang, Wei-Ming Ke, Chen-Yu Chuang, Jhih-Siao Huang, Wei-Su Wong, Ren-Song Tsay. 25-30 [doi]
• A unified instruction set programmable architecture for multi-standard advanced forward error correctionFrederik Naessens, Bruno Bougard, Siebert Bressinck, Lieven Hollevoet, Praveen Raghavan, Liesbet Van der Perre, Francky Catthoor. 31-36 [doi]
• A method for improving the efficiency of a two-level memory hierarchyRadomir Jakovljevic, Aleksandar Beric. 37-42 [doi]
• Hardware acceleration for tracking by computing low-order geometric momentsJulien A. Vijverberg, Peter H. N. de With. 43-48 [doi]
• Efficient image reconstruction using partial 2D Fourier transformLanping Deng, Chi-Li Yu, Chaitali Chakrabarti, Jungsub Kim, Vijay Narayanan. 49-54 [doi]
• Parallel channel interleavers for 3GPP2/UMBMohammad M. Mansour. 55-60 [doi]
• New simplified sum-product algorithm for low complexity LDPC decodingMyung Hun Lee, Jae Hee Han, Myung Hoon Sunwoo. 61-66 [doi]
• A systolic architecture of a Sequential Monte Carlo-based equalizer for frequency-selective MIMO channelsMahdi Shabany, P. Glenn Gulak. 67-72 [doi]
• Location-Constrained Particle Filter human positioning and tracking systemChih-Hao Chao, Chun-Yuan Chu, An-Yeu Wu. 73-76 [doi]
• Cooperative OFDM for energy-efficient wireless sensor networksWeiguo Tang, Lei Wang. 77-82 [doi]
• High-throughput dual-mode single/double binary map processor design for wireless wanChun-Yu Chen, Cheng-Hung Lin, An-Yeu Wu. 83-87 [doi]
• Trade-off analysis of decoding algorithms and architectures for multi-standard LDPC decoderRobert Priewasser, Mario Huemer, Bruno Bougard. 88-93 [doi]
• Error correction for multi-level NAND flash memory using Reed-Solomon codesBainan Chen, Xinmiao Zhang, Zhongfeng Wang. 94-99 [doi]
• Impact of roundoff error on the decisions of the Log Sum-Product algorithm for LDPC decodingNikos Kanistras, Vassilis Paliouras. 100-105 [doi]
• Two-dimensional crosstalk avoidance codesXuebin Wu, Zhiyuan Yan, Yuan Xie. 106-111 [doi]
• Multi-mode sub-Nyquist rate digital-to-analog conversion for direct waveform synthesisStanley Yuan-Shih Chen, Nam-Seog Kim, Jan M. Rabaey. 112-117 [doi]
• An implementation friendly low complexity multiplierless LLR generator for soft MIMO sphere decodersMin Li, David Novo, Bruno Bougard, Frederik Naessens, Liesbet Van der Perre, Francky Catthoor. 118-123 [doi]
• Reduced-complexity MSGR-based matrix inversionLei Ma, Kevin Dickson, John McAllister, John V. McCanny, Mathini Sellathurai. 124-128 [doi]
• Kalman filtering based motion estimation for video coding with adaptive block partitioningYi Luo, Mehmet Celenk. 129-134 [doi]
• Fast multiple reference frame selection methods for H.264/AVCShin Wang Ho, Sung Dae Kim, Myung Hoon Sunwoo. 135-139 [doi]
• Minimal complexity low-latency architectures for Viterbi decodersRenfei Liu, Keshab K. Parhi. 140-145 [doi]
• Efficient ordering schemes for sphere decoderYongmei Dai, Zhiyuan Yan. 146-151 [doi]
• Analysis of belief propagation for hardware realizationChao-Chung Cheng, Chia-Kai Liang, Yen-Chieh Lai, Homer H. Chen, Liang-Gee Chen. 152-157 [doi]
• Bio-inspired unified model of visual segmentation system for CAPTCHA character recognitionChi-Wei Lin, Yu-Han Chen, Liang-Gee Chen. 158-163 [doi]
• Video decoder reconfigurations and AVS extensions in the new MPEG reconfigurable video coding frameworkDandan Ding, Lu Yu, Christophe Lucarz, Marco Mattavelli. 164-169 [doi]
• On the verification of multi-standard SoC S for reconfigurable video coding based on algorithm/architecture co-explorationGwo Giun Lee, He-Yuan Lin, Ming-Jiun Wang, Bo-Han Chen, Yuan-Long Cheng. 170-175 [doi]
• Efficient realization of a cal video decoder on a mobile terminal (position paper)Carl von Platen, Johan Eker. 176-181 [doi]
• Scheduling of dataflow models within the Reconfigurable Video Coding frameworkJani Boutellier, Veeranjaneyulu Sadhanala, Christophe Lucarz, Philip Brisk, Marco Mattavelli. 182-187 [doi]
• Efficient data flow variable length decoding implementation for the MPEG reconfigurable video coding frameworkJianjun Li, Dandan Ding, Christophe Lucarz, Samuel Keller, Marco Mattavelli. 188-193 [doi]
• Defect-tolerant digital filtering with unreliable molecular electronicsShuo Wang, Jianwei Dai, Lei Wang. 194-199 [doi]
• Traffic-balanced IP mapping algorithm for 2D-mesh On-Chip-NetworksTing-Jung Lin, Shu-Yen Lin, An-Yeu Wu. 200-203 [doi]
• DSP implementation of probabilistic sound source localizationSeung Seob Yeom, JongSuk Choi, Yoon Seob Lim, Mignon Park. 204-209 [doi]
• Soft decoder architecture of LT codesKai Zhang, Xinming Huang, Chen Shen. 210-215 [doi]
• Low-complexity high-speed 4-D TCM decoderJinjin He, Zhongfeng Wang, Huaping Liu. 216-220 [doi]
• Error-resilient low-power Viterbi decoders via state clusteringRami A. Abdallah, Naresh R. Shanbhag. 221-226 [doi]
• Further cost reduction of adaptive echo and next cancellers for high-speed Ethernet transceiversJie Chen, Keshab K. Parhi. 227-232 [doi]
• Power efficient dynamic-range utilisation for DSP on FPGAStephen McKeown, Roger Woods, John McAllister. 233-238 [doi]
• Hierarchical run time deadlock detection in process networksBin Jiang, Ed F. Deprettere, Bart Kienhuis. 239-244 [doi]
• Application-driven adaptive fixed-point refinement for SDRsDavid Novo, Min Li, Bruno Bougard, Frederik Naessens, Liesbet Van der Perre, Francky Catthoor. 245-250 [doi]
• Low-complexity polynomials modulo integer with linearly incremented variablePerttu Salmela, Harri Sorokin, Jarmo Takala. 251-256 [doi]
• SmartCell: A power-efficient reconfigurable architecture for data streaming applicationsCao Liang, Xin-Ming Huang. 257-262 [doi]
• The support of software design patterns for streaming RPC on embedded multicore processorsKun-Yuan Hsieh, Yen-Chih Liu, Chi-Hua Lai, Jenq Kuen Lee. 263-268 [doi]
• Efficient mapping of advanced signal processing algorithms on multi-processor architecturesBhavana B. Manjunath, Aaron S. Williams, Chaitali Chakrabarti, Antonia Papandreou-Suppappola. 269-274 [doi]
• Parallelization of AdaBoost algorithm on multi-core processorsYen-Kuang Chen, Wenlong Li, Xiaofeng Tong. 275-280 [doi]
• Automatic software synthesis of dataflow program: An MPEG-4 simple profile decoder case studyGhislain Roquier, Matthieu Wipliez, Mickaël Raulet, Jörn W. Janneck, Ian D. Miller, David B. Parlour. 281-286 [doi]
• Synthesizing hardware from dataflow programs: An MPEG-4 simple profile decoder case studyJörn W. Janneck, Ian D. Miller, David B. Parlour, Ghislain Roquier, Matthieu Wipliez, Mickaël Raulet. 287-292 [doi]
• Validation of bitstream syntax and synthesis of parsers in the MPEG Reconfigurable Video Coding frameworkMickaël Raulet, Jonathan Piat, Christophe Lucarz, Marco Mattavelli. 293-298 [doi]