Aoxiang Tang - researchr alias

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Viewing Publication 1 - 5 from 5

2016

GenFin: Genetic Algorithm-Based Multiobjective Statistical Logic Circuit Optimization Using Incremental Statistical AnalysisAoxiang Tang, Niraj K. Jha. tvlsi, 24(3):1126-1139, 2016. [doi]

Delay/Power Modeling and Optimization of FinFET Circuit Modules under PVT Variations: Observing the Trends between the 22nm and 14nm Technology NodesAoxiang Tang, Xun Gao, Lung-Yen Chen, Niraj K. Jha. jetc, 12(4):42, 2016. [doi]

2015

McPAT-PVT: Delay and Power Modeling Framework for FinFET Processor Architectures Under PVT VariationsAoxiang Tang, Yang Yang, Chun-Yi Lee, Niraj K. Jha. tvlsi, 23(9):1616-1627, 2015. [doi]

2013

Thermal Characterization of Test Techniques for FinFET and 3D Integrated CircuitsAoxiang Tang, Niraj K. Jha. jetc, 9(1):6, 2013. [doi]

Design space exploration of FinFET cacheAoxiang Tang, Niraj K. Jha. jetc, 9(3):20, 2013. [doi]

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