Chen-Ting Ko - researchr alias

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Viewing Publication 1 - 2 from 2

2020

A 7-nm FinFET CMOS PLL With 388-fs Jitter and -80-dBc Reference Spur Featuring a Track-and-Hold Charge Pump and Automatic Loop Gain ControlChen-Ting Ko, Ting-Kuei Kuan, Ruei-Pin Shen, Chih-Hsien Chang. jssc, 55(4):1043-1050, 2020. [doi]

2019

A 387.6fs Integrated Jitter and -80dBc Reference Spurs Ring based PLL with Track- and-Hold Charge Pump and Automatic Loop Gain Control in 7nm FinFET CMOSChen-Ting Ko, Ting-Kuei Kuan, Ruei-Pin Shen, Chih-Hsien Chang, Kenny Hsieh, Mark Chen 0001. vlsic 2019: 164 [doi]

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