Ching-Tsun Chou - researchr alias

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Viewing Publication 1 - 23 from 23

2014

Revisiting the Complexity of Hardware Cache Coherence and Some ImplicationsRakesh Komuravelli, Sarita V. Adve, Ching-Tsun Chou. taco, 11(4):37, 2014. [doi]

2011

DeNovo: Rethinking the Memory Hierarchy for Disciplined ParallelismByn Choi, Rakesh Komuravelli, Hyojin Sung, Robert Smolinski, Nima Honarmand, Sarita V. Adve, Vikram S. Adve, Nicholas P. Carter, Ching-Tsun Chou. IEEEpact 2011: 155-166 [doi]

2010

Efficient methods for formally verifying safety properties of hierarchical cache coherence protocolsXiaofang Chen, Yu Yang, Ganesh Gopalakrishnan, Ching-Tsun Chou. fmsd, 36(1):37-64, 2010. [doi]

2007

Hierarchical cache coherence protocol verification one level at a time through assume guaranteeXiaofang Chen, Yu Yang, Michael Delisi, Ganesh Gopalakrishnan, Ching-Tsun Chou. hldvt 2007: 107-114 [doi]

2006

Reducing Verification Complexity of a Multicore Coherence Protocol Using Assume/GuaranteeXiaofang Chen, Yu Yang, Ganesh Gopalakrishnan, Ching-Tsun Chou. FMCAD 2006: 81-88 [doi]

2004

A Simple Method for Parameterized Verification of Cache Coherence ProtocolsChing-Tsun Chou, Phanindra K. Mannava, Seungjoon Park. FMCAD 2004: 382-398 [doi]

2003

Experience with Applying Formal Methods to Protocol Specification and System ArchitectureMani Azimi, Ching-Tsun Chou, Akhilesh Kumar, Victor W. Lee, Phanindra K. Mannava, Seungjoon Park. fmsd, 22(2):109-116, 2003. [doi]

2001

A Specification Methodology by a Collection of Compact Properties as Applied to the Intel:::®::: Itanium:::TM::: Processor Bus ProtocolKanna Shimizu, David L. Dill, Ching-Tsun Chou. charme 2001: 340-354 [doi]

1999

The Mathematical Foundation fo Symbolic Trajectory EvaluationChing-Tsun Chou. cav 1999: 196-207 [doi]

Formal Verification of a Partial-Order Reduction Technique for Model CheckingChing-Tsun Chou, Doron Peled. JAR, 23(3-4):265-298, 1999.

1996

Simple Proof Techniques for Property Preservation via SimulationChing-Tsun Chou. ipl, 60(3):129-134, 1996. [doi]

Formal Verification of a Partial-Order Reduction Technique for Model CheckingChing-Tsun Chou, Doron Peled. TACAS 1996: 241-257

1995

Mechanical Verification of Distributed Algorithms in Higher-Order LogicChing-Tsun Chou. cj, 38(2):152-161, 1995.

1994

A Formal Theory of Undirected Graphs in Higher-Order LogicChing-Tsun Chou. tphol 1994: 144-157

Mechanical Verification of Distributed Algorithms in Higher-Order LogicChing-Tsun Chou. tphol 1994: 158-176

1993

Predicates, Temporal Logic, and SimulationsChing-Tsun Chou. tphol 1994: 310-323

1992

A Note on Interactive Theorem Proving with Theorem Continuation FunctionsChing-Tsun Chou. tphol 1993: 59-69

A Sequent Formulation of a Logic of Predicates in HOLChing-Tsun Chou. tphol 1993: 71-80

1990

Synchronizing asynchronous bounded delay networksChing-Tsun Chou, Israel Cidon, Inder S. Gopal, Shmuel Zaks. tcom, 38(2):144-147, 1990. [doi]

1989

Linear Broadcast RoutingChing-Tsun Chou, Inder S. Gopal. jal, 10(4):490-517, 1989.

1988

Linear Broadcast RoutingChing-Tsun Chou. fsttcs 1988: 122

Understanding and Verifying Distributed Algorithms Using Stratified DecompositionChing-Tsun Chou, Eli Gafni. podc 1988: 44-65 [doi]

1987

Synchronizing Aysnchronous Bounded Delay NetworksChing-Tsun Chou, Israel Cidon, Inder S. Gopal, Shmuel Zaks. wdag 1988: 212-218

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