Abstract is missing.
- Reliable network-on-chip based on generalized de Bruijn graphMohammad Hosseinabady, Mohammad Reza Kakoee, Jimson Mathew, Dhiraj K. Pradhan. 3-10 [doi]
- Improving feasible interactions among multiple processesKiran Ramineni, Ian G. Harris, Shireesh Verma. 11-18 [doi]
- Framework for fast and accurate performance simulation of multiprocessor systemsEric Cheung, Harry Hsieh, Felice Balarin. 21-28 [doi]
- Automatic TLM generation for C-Based MPSoC designLucky L. Chi Yu Lo, Samar Abdi. 29-36 [doi]
- Automatic buffer sizing for rate-constrained KPN applications on multiprocessor system-on-chipEric Cheung, Harry Hsieh, Felice Balarin. 37-44 [doi]
- Post-silicon verification methodology on Sun's UItraSPARC T2Jai Kumar, Catherine Ahlschlager, Peter Isberg. 47 [doi]
- Challenges in post-silicon verification of IBM's Cell/B.E. and other game processorsShakti Kapoor. 48-52 [doi]
- Intel's Post Silicon functional validation approachTommy Bojan, Igor Frumkin, Robert Mauri. 53-56 [doi]
- Bug analysis and corresponding error models in real designsTao Lv, Tong Xu, Yang Zhao, Huawei Li, Xiaowei Li 0001. 59-64 [doi]
- Automatic error diagnosis and correction for RTL designsKai-Hui Chang, Ilya Wagner, Valeria Bertacco, Igor L. Markov. 65-72 [doi]
- Bridging RTL and gate: correlating different levels of abstraction for design debuggingEric Cheung, Xi Chen, Fur-Shing Tsai, Yu-Chin Hsu, Harry Hsieh. 73-80 [doi]
- Model-driven test generation for system level validationDeepak Mathaikutty, Sumit Ahuja, Ajit Dingankar, Sandeep K. Shukla. 83-90 [doi]
- Towards RTL test generation from SystemC TLM specificationsMingsong Chen, Prabhat Mishra, Dhrubajyoti Kalita. 91-96 [doi]
- A novel formal approach to generate high-level test vectors without ILP and SAT solversBijan Alizadeh, Masahiro Fujita. 97-104 [doi]
- Hierarchical cache coherence protocol verification one level at a time through assume guaranteeXiaofang Chen, Yu Yang, Michael Delisi, Ganesh Gopalakrishnan, Ching-Tsun Chou. 107-114 [doi]
- Formal model construction using HDL simulation semanticsJoseph Buck, Dong Wang, Yunshan Zhu. 115-122 [doi]
- An approach for computing the initial state for retimed synchronous sequential circuitsNoureddine Chabini, Wayne Wolf. 123-130 [doi]
- Circuit design and verication with Esterel v7 and Esterel StudioGérard Berry. 133-136 [doi]
- FFT Compiler: from math to efficient hardware HLDVT invited short paperPeter A. Milder, Franz Franchetti, James C. Hoe, Markus Püschel. 137-139 [doi]
- Transactors for parallel hardware and software co-designKrste Asanovic. 140-142 [doi]
- Functional coverage measurements and results in post-Silicon validation of Core™2 duo familyTommy Bojan, Manuel Aguilar Arreola, Eran Shlomo, Tal Shachar. 145-150 [doi]
- Coverage-directed test generation through automatic constraint extractionOnur Guzey, Li-C. Wang. 151-158 [doi]
- Automatic generation of functional coverage models from CTLShireesh Verma, Ian G. Harris, Kiran Ramineni. 159-164 [doi]
- Panel: Unified approach leading to a seamlessly evolving test bench for all phases of a multi-core design, validation and production testSunil Kakkar, Janick Bergeron, Brian Bailey, Harry Foster, Ian Harris. 167-168 [doi]
- Automating the IEEE std.1500 compliance verification for embedded coresAlfredo Benso, Stefano Di Carlo, Paolo Prinetto, Alberto Bosio. 171-178 [doi]
- Validating the dependability of embedded systems through fault injection by means of loadable kernel modulesMarco Murciano, Massimo Violante. 179-186 [doi]
- AME: an abstract middleware environment for validating networked embedded systems applicationsFranco Fummi, Giovanni Perbellini, Davide Quaglia, Sara Vinco. 187-194 [doi]