Dengjie Wang - researchr alias

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Viewing Publication 1 - 6 from 6

2022

A 56-Gbps PAM-4 Wireline Receiver With 4-Tap Direct DFE Employing Dynamic CML Comparators in 65 nm CMOSDengjie Wang, Ziqiang Wang, Hao Xu, Jiawei Wang, Zeliang Zhao, Chun Zhang, Zhihua Wang 0001, Hong Chen 0002. tcasI, 69(3):1027-1040, 2022. [doi]

2021

An 11.05 mW/Gbps Quad-Channel 1.25-10.3125 Gbps Serial Transceiver With a 2-Tap Adaptive DFE and a 3-Tap Transmit FFE in 40 nm CMOSHong Chen 0002, Dengjie Wang, Ziqiang Wang, Shuai Yuan 0005, Chun Zhang, Zhihua Wang 0001. access, 9:70856-70867, 2021. [doi]

A 40 Gbps PAM-4 Receiver with 12-Tap Direct Decision Feedback Equalizer Employing 1.5-stage Slicers in 65-nm CMOSZeliang Zhao, Xin Wu, Dengjie Wang, Ziqiang Wang, Chun Zhang, Xiangyu Li, Zhihua Wang 0001. icta3 2021: 230-231 [doi]

2019

A 4-40 Gb/s PAM-4 transmitter with a hybrid driver in 65 nm CMOS technologyDengjie Wang, Hong Chen, Wenhuan Luan, Xin Lin, Fangxu Lv, Ziqiang Wang, Hanjun Jiang, Chun Zhang, Zhihua Wang. mwscas 2019: 251-254 [doi]

2018

A 47mW Two-Dimensional Eye Opening Monitor for Multi-Protocol SerDesWenhuan Luan, Ting Chen, Shuai Yuan, Peijie Li, Ziqiang Wang, Xin Lin, Mao Li, Dengjie Wang, Hong Chen. mwscas 2018: 121-124 [doi]

2017

Design of 56 Gb/s PAM4 wire-line receiver with ring VCO based CDR in a 65 nm CMOS technologyFangxu Lv, Jianye Wang, Dengjie Wang, Yongcong Liu, Ziqiang Wang. asicon 2017: 537-540 [doi]

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